Commit c4a7bf54 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging 



# gpg: Signature made Fri 06 Nov 2015 20:01:44 GMT using RSA key ID AAFC390E
# gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>"

* remotes/jnsnow/tags/ide-pull-request:
  arm: allwinner-a10: Add SATA
  ahci: Add allwinner AHCI
  ahci: split realize and init
  ahci: Add some MMIO debug printfs
  ide: remove hardcoded 2GiB transactional limit

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 4b59f39b dca62576

hw/arm/allwinner-a10.c

+11 −0
Original line number Diff line number Diff line
@@ -39,6 +39,9 @@ static void aw_a10_init(Object *obj) 
        qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);

        qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);

    }



    object_initialize(&s->sata, sizeof(s->sata), TYPE_ALLWINNER_AHCI);

    qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());

}



static void aw_a10_realize(DeviceState *dev, Error **errp)
@@ -93,6 +96,14 @@ static void aw_a10_realize(DeviceState *dev, Error **errp) 
    sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);

    sysbus_connect_irq(sysbusdev, 0, s->irq[55]);



    object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]);



    /* FIXME use a qdev chardev prop instead of serial_hds[] */

    serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1],

                   115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);

hw/ide/ahci.c

+147 −35
Original line number Diff line number Diff line
@@ -378,17 +378,23 @@ static uint64_t ahci_mem_read(void *opaque, hwaddr addr, unsigned size) 
    int ofst = addr - aligned;

    uint64_t lo = ahci_mem_read_32(opaque, aligned);

    uint64_t hi;

    uint64_t val;



    /* if < 8 byte read does not cross 4 byte boundary */

    if (ofst + size <= 4) {

        return lo >> (ofst * 8);

    }

        val = lo >> (ofst * 8);

    } else {

        g_assert_cmpint(size, >, 1);



        /* If the 64bit read is unaligned, we will produce undefined

         * results. AHCI does not support unaligned 64bit reads. */

        hi = ahci_mem_read_32(opaque, aligned + 4);

    return (hi << 32 | lo) >> (ofst * 8);

        val = (hi << 32 | lo) >> (ofst * 8);

    }



    DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",

            addr, val, size);

    return val;

}
@@ -397,6 +403,9 @@ static void ahci_mem_write(void *opaque, hwaddr addr, 
{

    AHCIState *s = opaque;



    DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",

            addr, val, size);



    /* Only aligned reads are allowed on AHCI */

    if (addr & 3) {

        fprintf(stderr, "ahci: Mis-aligned write to addr 0x"
@@ -804,8 +813,21 @@ static int prdt_tbl_entry_size(const AHCI_SG *tbl) 
    return (le32_to_cpu(tbl->flags_size) & AHCI_PRDT_SIZE_MASK) + 1;

}



/**

 * Fetch entries in a guest-provided PRDT and convert it into a QEMU SGlist.

 * @ad: The AHCIDevice for whom we are building the SGList.

 * @sglist: The SGList target to add PRD entries to.

 * @cmd: The AHCI Command Header that describes where the PRDT is.

 * @limit: The remaining size of the S/ATA transaction, in bytes.

 * @offset: The number of bytes already transferred, in bytes.

 *

 * The AHCI PRDT can describe up to 256GiB. S/ATA only support transactions of

 * up to 32MiB as of ATA8-ACS3 rev 1b, assuming a 512 byte sector size. We stop

 * building the sglist from the PRDT as soon as we hit @limit bytes,

 * which is <= INT32_MAX/2GiB.

 */

static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist,

                                AHCICmdHdr *cmd, int64_t limit, int32_t offset)

                                AHCICmdHdr *cmd, int64_t limit, uint64_t offset)

{

    uint16_t opts = le16_to_cpu(cmd->opts);

    uint16_t prdtl = le16_to_cpu(cmd->prdtl);
@@ -823,14 +845,6 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, 
    IDEBus *bus = &ad->port;

    BusState *qbus = BUS(bus);



    /*

     * Note: AHCI PRDT can describe up to 256GiB. SATA/ATA only support

     * transactions of up to 32MiB as of ATA8-ACS3 rev 1b, assuming a

     * 512 byte sector size. We limit the PRDT in this implementation to

     * a reasonably large 2GiB, which can accommodate the maximum transfer

     * request for sector sizes up to 32K.

     */



    if (!prdtl) {

        DPRINTF(ad->port_no, "no sg list given by guest: 0x%08x\n", opts);

        return -1;
@@ -880,13 +894,6 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, 
            qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr),

                            MIN(prdt_tbl_entry_size(&tbl[i]),

                                limit - sglist->size));

            if (sglist->size > INT32_MAX) {

                error_report("AHCI Physical Region Descriptor Table describes "

                             "more than 2 GiB.");

                qemu_sglist_destroy(sglist);

                r = -1;

                goto out;

            }

        }

    }
@@ -1427,24 +1434,26 @@ static const IDEDMAOps ahci_dma_ops = { 
    .cmd_done = ahci_cmd_done,

};



void ahci_init(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)

void ahci_init(AHCIState *s, DeviceState *qdev)

{

    qemu_irq *irqs;

    int i;



    s->as = as;

    s->ports = ports;

    s->dev = g_new0(AHCIDevice, ports);

    s->container = qdev;

    ahci_reg_init(s);

    /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */

    memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s,

                          "ahci", AHCI_MEM_BAR_SIZE);

    memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s,

                          "ahci-idp", 32);

}



    irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports);

void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)

{

    qemu_irq *irqs;

    int i;



    s->as = as;

    s->ports = ports;

    s->dev = g_new0(AHCIDevice, ports);

    ahci_reg_init(s);

    irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports);

    for (i = 0; i < s->ports; i++) {

        AHCIDevice *ad = &s->dev[i];
@@ -1639,17 +1648,24 @@ static void sysbus_ahci_reset(DeviceState *dev) 
    ahci_reset(&s->ahci);

}



static void sysbus_ahci_realize(DeviceState *dev, Error **errp)

static void sysbus_ahci_init(Object *obj)

{

    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);

    SysbusAHCIState *s = SYSBUS_AHCI(dev);

    SysbusAHCIState *s = SYSBUS_AHCI(obj);

    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);



    ahci_init(&s->ahci, dev, &address_space_memory, s->num_ports);

    ahci_init(&s->ahci, DEVICE(obj));



    sysbus_init_mmio(sbd, &s->ahci.mem);

    sysbus_init_irq(sbd, &s->ahci.irq);

}



static void sysbus_ahci_realize(DeviceState *dev, Error **errp)

{

    SysbusAHCIState *s = SYSBUS_AHCI(dev);



    ahci_realize(&s->ahci, dev, &address_space_memory, s->num_ports);

}



static Property sysbus_ahci_properties[] = {

    DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1),

    DEFINE_PROP_END_OF_LIST(),
@@ -1670,12 +1686,108 @@ static const TypeInfo sysbus_ahci_info = { 
    .name          = TYPE_SYSBUS_AHCI,

    .parent        = TYPE_SYS_BUS_DEVICE,

    .instance_size = sizeof(SysbusAHCIState),

    .instance_init = sysbus_ahci_init,

    .class_init    = sysbus_ahci_class_init,

};



#define ALLWINNER_AHCI_BISTAFR    ((0xa0 - ALLWINNER_AHCI_MMIO_OFF) / 4)

#define ALLWINNER_AHCI_BISTCR     ((0xa4 - ALLWINNER_AHCI_MMIO_OFF) / 4)

#define ALLWINNER_AHCI_BISTFCTR   ((0xa8 - ALLWINNER_AHCI_MMIO_OFF) / 4)

#define ALLWINNER_AHCI_BISTSR     ((0xac - ALLWINNER_AHCI_MMIO_OFF) / 4)

#define ALLWINNER_AHCI_BISTDECR   ((0xb0 - ALLWINNER_AHCI_MMIO_OFF) / 4)

#define ALLWINNER_AHCI_DIAGNR0    ((0xb4 - ALLWINNER_AHCI_MMIO_OFF) / 4)

#define ALLWINNER_AHCI_DIAGNR1    ((0xb8 - ALLWINNER_AHCI_MMIO_OFF) / 4)

#define ALLWINNER_AHCI_OOBR       ((0xbc - ALLWINNER_AHCI_MMIO_OFF) / 4)

#define ALLWINNER_AHCI_PHYCS0R    ((0xc0 - ALLWINNER_AHCI_MMIO_OFF) / 4)

#define ALLWINNER_AHCI_PHYCS1R    ((0xc4 - ALLWINNER_AHCI_MMIO_OFF) / 4)

#define ALLWINNER_AHCI_PHYCS2R    ((0xc8 - ALLWINNER_AHCI_MMIO_OFF) / 4)

#define ALLWINNER_AHCI_TIMER1MS   ((0xe0 - ALLWINNER_AHCI_MMIO_OFF) / 4)

#define ALLWINNER_AHCI_GPARAM1R   ((0xe8 - ALLWINNER_AHCI_MMIO_OFF) / 4)

#define ALLWINNER_AHCI_GPARAM2R   ((0xec - ALLWINNER_AHCI_MMIO_OFF) / 4)

#define ALLWINNER_AHCI_PPARAMR    ((0xf0 - ALLWINNER_AHCI_MMIO_OFF) / 4)

#define ALLWINNER_AHCI_TESTR      ((0xf4 - ALLWINNER_AHCI_MMIO_OFF) / 4)

#define ALLWINNER_AHCI_VERSIONR   ((0xf8 - ALLWINNER_AHCI_MMIO_OFF) / 4)

#define ALLWINNER_AHCI_IDR        ((0xfc - ALLWINNER_AHCI_MMIO_OFF) / 4)

#define ALLWINNER_AHCI_RWCR       ((0xfc - ALLWINNER_AHCI_MMIO_OFF) / 4)



static uint64_t allwinner_ahci_mem_read(void *opaque, hwaddr addr,

                                        unsigned size)

{

    AllwinnerAHCIState *a = opaque;

    uint64_t val = a->regs[addr/4];



    switch (addr / 4) {

    case ALLWINNER_AHCI_PHYCS0R:

        val |= 0x2 << 28;

        break;

    case ALLWINNER_AHCI_PHYCS2R:

        val &= ~(0x1 << 24);

        break;

    }

    DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",

            addr, val, size);

    return  val;

}



static void allwinner_ahci_mem_write(void *opaque, hwaddr addr,

                                     uint64_t val, unsigned size)

{

    AllwinnerAHCIState *a = opaque;



    DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",

            addr, val, size);

    a->regs[addr/4] = val;

}



static const MemoryRegionOps allwinner_ahci_mem_ops = {

    .read = allwinner_ahci_mem_read,

    .write = allwinner_ahci_mem_write,

    .valid.min_access_size = 4,

    .valid.max_access_size = 4,

    .endianness = DEVICE_LITTLE_ENDIAN,

};



static void allwinner_ahci_init(Object *obj)

{

    SysbusAHCIState *s = SYSBUS_AHCI(obj);

    AllwinnerAHCIState *a = ALLWINNER_AHCI(obj);



    memory_region_init_io(&a->mmio, OBJECT(obj), &allwinner_ahci_mem_ops, a,

                          "allwinner-ahci", ALLWINNER_AHCI_MMIO_SIZE);

    memory_region_add_subregion(&s->ahci.mem, ALLWINNER_AHCI_MMIO_OFF,

                                &a->mmio);

}



static const VMStateDescription vmstate_allwinner_ahci = {

    .name = "allwinner-ahci",

    .version_id = 1,

    .minimum_version_id = 1,

    .fields = (VMStateField[]) {

        VMSTATE_UINT32_ARRAY(regs, AllwinnerAHCIState,

                             ALLWINNER_AHCI_MMIO_SIZE/4),

        VMSTATE_END_OF_LIST()

    }

};



static void allwinner_ahci_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);



    dc->vmsd = &vmstate_allwinner_ahci;

}



static const TypeInfo allwinner_ahci_info = {

    .name          = TYPE_ALLWINNER_AHCI,

    .parent        = TYPE_SYSBUS_AHCI,

    .instance_size = sizeof(AllwinnerAHCIState),

    .instance_init = allwinner_ahci_init,

    .class_init    = allwinner_ahci_class_init,

};



static void sysbus_ahci_register_types(void)

{

    type_register_static(&sysbus_ahci_info);

    type_register_static(&allwinner_ahci_info);

}



type_init(sysbus_ahci_register_types)

hw/ide/ahci.h

+18 −1
Original line number Diff line number Diff line
@@ -366,7 +366,8 @@ typedef struct SDBFIS { 
    uint32_t payload;

} QEMU_PACKED SDBFIS;



void ahci_init(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports);

void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports);

void ahci_init(AHCIState *s, DeviceState *qdev);

void ahci_uninit(AHCIState *s);



void ahci_reset(AHCIState *s);
@@ -385,4 +386,20 @@ typedef struct SysbusAHCIState { 
    uint32_t num_ports;

} SysbusAHCIState;



#define TYPE_ALLWINNER_AHCI "allwinner-ahci"

#define ALLWINNER_AHCI(obj) OBJECT_CHECK(AllwinnerAHCIState, (obj), \

                       TYPE_ALLWINNER_AHCI)



#define ALLWINNER_AHCI_MMIO_OFF  0x80

#define ALLWINNER_AHCI_MMIO_SIZE 0x80



struct AllwinnerAHCIState {

    /*< private >*/

    SysbusAHCIState parent_obj;

    /*< public >*/



    MemoryRegion mmio;

    uint32_t regs[ALLWINNER_AHCI_MMIO_SIZE/4];

};



#endif /* HW_IDE_AHCI_H */

hw/ide/ich.c

+9 −1
Original line number Diff line number Diff line
@@ -97,6 +97,13 @@ static void pci_ich9_reset(DeviceState *dev) 
    ahci_reset(&d->ahci);

}



static void pci_ich9_ahci_init(Object *obj)

{

    struct AHCIPCIState *d = ICH_AHCI(obj);



    ahci_init(&d->ahci, DEVICE(obj));

}



static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp)

{

    struct AHCIPCIState *d;
@@ -104,7 +111,7 @@ static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp) 
    uint8_t *sata_cap;

    d = ICH_AHCI(dev);



    ahci_init(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);

    ahci_realize(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);



    pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1);
@@ -171,6 +178,7 @@ static const TypeInfo ich_ahci_info = { 
    .name          = TYPE_ICH9_AHCI,

    .parent        = TYPE_PCI_DEVICE,

    .instance_size = sizeof(AHCIPCIState),

    .instance_init = pci_ich9_ahci_init,

    .class_init    = ich_ahci_class_init,

};

hw/ide/internal.h

+1 −1
Original line number Diff line number Diff line
@@ -397,7 +397,7 @@ struct IDEState { 
    struct iovec iov;

    QEMUIOVector qiov;

    /* ATA DMA state */

    int32_t io_buffer_offset;

    uint64_t io_buffer_offset;

    int32_t io_buffer_size;

    QEMUSGList sg;

    /* PIO transfer handling */