Commit c3affe56 authored by Andreas Färber's avatar Andreas Färber
Browse files

cpu: Pass CPUState to cpu_interrupt() 



Move it to qom/cpu.h to avoid issues with include order.

Change pc_acpi_smi_interrupt() opaque to X86CPU.

Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
parent d8ed887b

cpus.c

+1 −1
Original line number Diff line number Diff line
@@ -1309,7 +1309,7 @@ void qmp_inject_nmi(Error **errp) 


    for (env = first_cpu; env != NULL; env = env->next_cpu) {

        if (!env->apic_state) {

            cpu_interrupt(env, CPU_INTERRUPT_NMI);

            cpu_interrupt(CPU(x86_env_get_cpu(env)), CPU_INTERRUPT_NMI);

        } else {

            apic_deliver_nmi(env->apic_state);

        }

exec.c

+1 −1
Original line number Diff line number Diff line
@@ -1467,7 +1467,7 @@ static void check_watchpoint(int offset, int len_mask, int flags) 
        /* We re-entered the check after replacing the TB. Now raise

         * the debug interrupt so that is will trigger after the

         * current instruction. */

        cpu_interrupt(env, CPU_INTERRUPT_DEBUG);

        cpu_interrupt(ENV_GET_CPU(env), CPU_INTERRUPT_DEBUG);

        return;

    }

    vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset;

hw/alpha_typhoon.c

+4 −6
Original line number Diff line number Diff line
@@ -62,10 +62,9 @@ static void cpu_irq_change(AlphaCPU *cpu, uint64_t req) 
{

    /* If there are any non-masked interrupts, tell the cpu.  */

    if (cpu != NULL) {

        CPUAlphaState *env = &cpu->env;

        CPUState *cs = CPU(cpu);

        if (req) {

            cpu_interrupt(env, CPU_INTERRUPT_HARD);

            cpu_interrupt(cs, CPU_INTERRUPT_HARD);

        } else {

            cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);

        }
@@ -359,11 +358,10 @@ static void cchip_write(void *opaque, hwaddr addr, 
            for (i = 0; i < 4; ++i) {

                AlphaCPU *cpu = s->cchip.cpu[i];

                if (cpu != NULL) {

                    CPUAlphaState *env = &cpu->env;

                    CPUState *cs = CPU(cpu);

                    /* IPI can be either cleared or set by the write.  */

                    if (newval & (1 << (i + 8))) {

                        cpu_interrupt(env, CPU_INTERRUPT_SMP);

                        cpu_interrupt(cs, CPU_INTERRUPT_SMP);

                    } else {

                        cpu_reset_interrupt(cs, CPU_INTERRUPT_SMP);

                    }
@@ -687,7 +685,7 @@ static void typhoon_set_timer_irq(void *opaque, int irq, int level) 
                /* Set the ITI bit for this cpu.  */

                s->cchip.misc |= 1 << (i + 4);

                /* And signal the interrupt.  */

                cpu_interrupt(&cpu->env, CPU_INTERRUPT_TIMER);

                cpu_interrupt(CPU(cpu), CPU_INTERRUPT_TIMER);

            }

        }

    }
@@ -700,7 +698,7 @@ static void typhoon_alarm_timer(void *opaque) 


    /* Set the ITI bit for this cpu.  */

    s->cchip.misc |= 1 << (cpu + 4);

    cpu_interrupt(&s->cchip.cpu[cpu]->env, CPU_INTERRUPT_TIMER);

    cpu_interrupt(CPU(s->cchip.cpu[cpu]), CPU_INTERRUPT_TIMER);

}



PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,

hw/apic.c

+11 −10
Original line number Diff line number Diff line
@@ -151,15 +151,15 @@ static void apic_local_deliver(APICCommonState *s, int vector) 


    switch ((lvt >> 8) & 7) {

    case APIC_DM_SMI:

        cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_SMI);

        cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SMI);

        break;



    case APIC_DM_NMI:

        cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_NMI);

        cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_NMI);

        break;



    case APIC_DM_EXTINT:

        cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);

        cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD);

        break;



    case APIC_DM_FIXED:
@@ -248,20 +248,20 @@ static void apic_bus_deliver(const uint32_t *deliver_bitmask, 


        case APIC_DM_SMI:

            foreach_apic(apic_iter, deliver_bitmask,

                cpu_interrupt(&apic_iter->cpu->env, CPU_INTERRUPT_SMI)

                cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_SMI)

            );

            return;



        case APIC_DM_NMI:

            foreach_apic(apic_iter, deliver_bitmask,

                cpu_interrupt(&apic_iter->cpu->env, CPU_INTERRUPT_NMI)

                cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_NMI)

            );

            return;



        case APIC_DM_INIT:

            /* normal INIT IPI sent to processors */

            foreach_apic(apic_iter, deliver_bitmask,

                         cpu_interrupt(&apic_iter->cpu->env,

                         cpu_interrupt(CPU(apic_iter->cpu),

                                       CPU_INTERRUPT_INIT)

            );

            return;
@@ -363,15 +363,16 @@ static int apic_irq_pending(APICCommonState *s) 
/* signal the CPU if an irq is pending */

static void apic_update_irq(APICCommonState *s)

{

    CPUState *cpu = CPU(s->cpu);

    CPUState *cpu;



    if (!(s->spurious_vec & APIC_SV_ENABLE)) {

        return;

    }

    cpu = CPU(s->cpu);

    if (!qemu_cpu_is_self(cpu)) {

        cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_POLL);

        cpu_interrupt(cpu, CPU_INTERRUPT_POLL);

    } else if (apic_irq_pending(s) > 0) {

        cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);

        cpu_interrupt(cpu, CPU_INTERRUPT_HARD);

    }

}
@@ -478,7 +479,7 @@ static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, 
static void apic_startup(APICCommonState *s, int vector_num)

{

    s->sipi_vector = vector_num;

    cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_SIPI);

    cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);

}



void apic_sipi(DeviceState *d)

hw/arm/omap1.c

+2 −2
Original line number Diff line number Diff line
@@ -1523,7 +1523,7 @@ static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, 
    omap_clk clk;



    if (value & (1 << 11)) {                            /* SETARM_IDLE */

        cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT);

        cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);

    }

    if (!(value & (1 << 10)))				/* WKUP_MODE */

        qemu_system_shutdown_request();	/* XXX: disable wakeup from IRQ */
@@ -3759,7 +3759,7 @@ void omap_mpu_wakeup(void *opaque, int irq, int req) 
    CPUState *cpu = CPU(mpu->cpu);



    if (cpu->halted) {

        cpu_interrupt(&mpu->cpu->env, CPU_INTERRUPT_EXITTB);

        cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);

    }

}