Loading target/xtensa/cpu.c +2 −1 Original line number Diff line number Diff line Loading @@ -47,7 +47,7 @@ static bool xtensa_cpu_has_work(CPUState *cs) { XtensaCPU *cpu = XTENSA_CPU(cs); return cpu->env.pending_irq_level; return !cpu->env.runstall && cpu->env.pending_irq_level; } /* CPUClass::reset() */ Loading @@ -74,6 +74,7 @@ static void xtensa_cpu_reset(CPUState *s) env->pending_irq_level = 0; reset_mmu(env); s->halted = env->runstall; } static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) Loading target/xtensa/cpu.h +2 −1 Original line number Diff line number Diff line Loading @@ -366,7 +366,7 @@ typedef struct CPUXtensaState { xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE]; unsigned autorefill_idx; bool runstall; int pending_irq_level; /* level of last raised IRQ */ void **irq_inputs; QEMUTimer *ccompare_timer; Loading Loading @@ -469,6 +469,7 @@ static inline void xtensa_select_static_vectors(CPUXtensaState *env, assert(n < 2); env->static_vectors = n; } void xtensa_runstall(CPUXtensaState *env, bool runstall); #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) #define XTENSA_OPTION_ALL (~(uint64_t)0) Loading target/xtensa/helper.c +13 −0 Original line number Diff line number Diff line Loading @@ -728,3 +728,16 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env) cpu_fprintf(f, "No TLB for this CPU core\n"); } } void xtensa_runstall(CPUXtensaState *env, bool runstall) { CPUState *cpu = CPU(xtensa_env_get_cpu(env)); env->runstall = runstall; cpu->halted = runstall; if (runstall) { cpu_interrupt(cpu, CPU_INTERRUPT_HALT); } else { cpu_reset_interrupt(cpu, CPU_INTERRUPT_HALT); } } Loading
target/xtensa/cpu.c +2 −1 Original line number Diff line number Diff line Loading @@ -47,7 +47,7 @@ static bool xtensa_cpu_has_work(CPUState *cs) { XtensaCPU *cpu = XTENSA_CPU(cs); return cpu->env.pending_irq_level; return !cpu->env.runstall && cpu->env.pending_irq_level; } /* CPUClass::reset() */ Loading @@ -74,6 +74,7 @@ static void xtensa_cpu_reset(CPUState *s) env->pending_irq_level = 0; reset_mmu(env); s->halted = env->runstall; } static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) Loading
target/xtensa/cpu.h +2 −1 Original line number Diff line number Diff line Loading @@ -366,7 +366,7 @@ typedef struct CPUXtensaState { xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE]; unsigned autorefill_idx; bool runstall; int pending_irq_level; /* level of last raised IRQ */ void **irq_inputs; QEMUTimer *ccompare_timer; Loading Loading @@ -469,6 +469,7 @@ static inline void xtensa_select_static_vectors(CPUXtensaState *env, assert(n < 2); env->static_vectors = n; } void xtensa_runstall(CPUXtensaState *env, bool runstall); #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) #define XTENSA_OPTION_ALL (~(uint64_t)0) Loading
target/xtensa/helper.c +13 −0 Original line number Diff line number Diff line Loading @@ -728,3 +728,16 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env) cpu_fprintf(f, "No TLB for this CPU core\n"); } } void xtensa_runstall(CPUXtensaState *env, bool runstall) { CPUState *cpu = CPU(xtensa_env_get_cpu(env)); env->runstall = runstall; cpu->halted = runstall; if (runstall) { cpu_interrupt(cpu, CPU_INTERRUPT_HALT); } else { cpu_reset_interrupt(cpu, CPU_INTERRUPT_HALT); } }