Commit bb238210 authored by Yongbok Kim's avatar Yongbok Kim Committed by Leon Alrae
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target-mips: add SIGRIE instruction 



Add SIGRIE (Signal Reserved Instruction Exception) for both MIPS and
microMIPS.
The instruction allows to use the 16-bit code field for software use.
This instruction is introduced by and required as of Release 6.

Signed-off-by: default avatarYongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: default avatarLeon Alrae <leon.alrae@imgtec.com>
Signed-off-by: default avatarLeon Alrae <leon.alrae@imgtec.com>
parent 35ac9e34

target-mips/translate.c

+11 −1
Original line number Diff line number Diff line
@@ -323,6 +323,7 @@ enum { 
    OPC_TLTIU    = (0x0B << 16) | OPC_REGIMM,

    OPC_TEQI     = (0x0C << 16) | OPC_REGIMM,

    OPC_TNEI     = (0x0E << 16) | OPC_REGIMM,

    OPC_SIGRIE   = (0x17 << 16) | OPC_REGIMM,

    OPC_SYNCI    = (0x1F << 16) | OPC_REGIMM,









    OPC_DAHI     = (0x06 << 16) | OPC_REGIMM,








@@ -12031,7 +12032,8 @@ enum {







    LSA = 0x0f,









    ALIGN = 0x1f,









    EXT = 0x2c,









    POOL32AXF = 0x3c









    POOL32AXF = 0x3c,









    SIGRIE = 0x3f









};

















/* POOL32AXF encoding of minor opcode field extension */








@@ -13655,6 +13657,10 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)







        case BREAK32:









            generate_exception_end(ctx, EXCP_BREAK);









            break;









        case SIGRIE:









            check_insn(ctx, ISA_MIPS32R6);









            generate_exception_end(ctx, EXCP_RI);









            break;









        default:









        pool32a_invalid:









                MIPS_INVAL("pool32a");








@@ -18973,6 +18979,10 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)







            check_insn_opc_removed(ctx, ISA_MIPS32R6);









            gen_trap(ctx, op1, rs, -1, imm);









            break;









        case OPC_SIGRIE:









            check_insn(ctx, ISA_MIPS32R6);









            generate_exception_end(ctx, EXCP_RI);









            break;









        case OPC_SYNCI:









            check_insn(ctx, ISA_MIPS32R2);









            /* Break the TB to be able to sync copied instructions