Commit 35ac9e34 authored by Yongbok Kim's avatar Yongbok Kim Committed by Leon Alrae
Browse files

target-mips: Set Config5.XNP for R6 cores 



Set Config5.XNP for R6 cores to indicate the extended LL/SC family
of instructions NOT present.

Signed-off-by: default avatarYongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: default avatarLeon Alrae <leon.alrae@imgtec.com>
Signed-off-by: default avatarLeon Alrae <leon.alrae@imgtec.com>
parent b00c7218

target-mips/translate_init.c

+2 −2
Original line number Diff line number Diff line
@@ -447,7 +447,7 @@ static const mips_def_t mips_defs[] = 
                       (1 << CP0C3_RXI) | (1U << CP0C3_M),

        .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |

                       (3 << CP0C4_IE) | (1U << CP0C4_M),

        .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_LLB),

        .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),

        .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |

                                  (1 << CP0C5_UFE),

        .CP0_LLAddr_rw_bitmask = 0,
@@ -665,7 +665,7 @@ static const mips_def_t mips_defs[] = 
                       (1 << CP0C3_RXI) | (1 << CP0C3_LPA),

        .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |

                       (0xfc << CP0C4_KScrExist),

        .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_LLB),

        .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),

        .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |

                                  (1 << CP0C5_FRE) | (1 << CP0C5_UFE),

        .CP0_LLAddr_rw_bitmask = 0,