Commit b894c6ed authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.1-20200507' into staging 



ppc patch queue for 2020-04-07

First pull request for qemu-5.1.  This includes:
 * Removal of all remaining cases where we had CAS triggered reboots
 * A number of improvements to NMI injection
 * Support for partition scoped radix translation in softmmu
 * Some fixes for NVDIMM handling
 * A handful of other minor fixes

# gpg: Signature made Thu 07 May 2020 06:00:55 BST
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full]
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-5.1-20200507:
  target-ppc: fix rlwimi, rlwinm, rlwnm for Clang-9
  spapr_nvdimm: Tweak error messages
  spapr_nvdimm.c: make 'label-size' mandatory
  target/ppc: Add support for Radix partition-scoped translation
  target/ppc: Rework ppc_radix64_walk_tree() for partition-scoped translation
  target/ppc: Extend ppc_radix64_check_prot() with a 'partition_scoped' bool
  target/ppc: Introduce ppc_radix64_xlate() for Radix tree translation
  spapr: Don't allow unplug of NVLink2 devices
  target/ppc: Assert if HV mode is set when running under a pseries machine
  target/ppc: Introduce a relocation bool in ppc_radix64_handle_mmu_fault()
  target/ppc: Enforce that the root page directory size must be at least 5
  spapr: Drop CAS reboot flag
  spapr/cas: Separate CAS handling from rebuilding the FDT
  spapr: Simplify selection of radix/hash during CAS
  ppc/pnv: Add support for NMI interface
  ppc/spapr: tweak change system reset helper
  spapr: Don't check capabilities removed between CAS calls
  target/ppc: Improve syscall exception logging

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 609dd53d c4f6a4a3

hw/ppc/pnv.c

+29 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ 
#include "sysemu/runstate.h"

#include "sysemu/cpus.h"

#include "sysemu/device_tree.h"

#include "sysemu/hw_accel.h"

#include "target/ppc/cpu.h"

#include "qemu/log.h"

#include "hw/ppc/fdt.h"
@@ -34,6 +35,7 @@ 
#include "hw/ppc/pnv.h"

#include "hw/ppc/pnv_core.h"

#include "hw/loader.h"

#include "hw/nmi.h"

#include "exec/address-spaces.h"

#include "qapi/visitor.h"

#include "monitor/monitor.h"
@@ -1977,10 +1979,35 @@ static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 
    }

}



static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)

{

    PowerPCCPU *cpu = POWERPC_CPU(cs);

    CPUPPCState *env = &cpu->env;



    cpu_synchronize_state(cs);

    ppc_cpu_do_system_reset(cs);

    /*

     * SRR1[42:45] is set to 0100 which the ISA defines as implementation

     * dependent. POWER processors use this for xscom triggered interrupts,

     * which come from the BMC or NMI IPIs.

     */

    env->spr[SPR_SRR1] |= PPC_BIT(43);

}



static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)

{

    CPUState *cs;



    CPU_FOREACH(cs) {

        async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);

    }

}



static void pnv_machine_class_init(ObjectClass *oc, void *data)

{

    MachineClass *mc = MACHINE_CLASS(oc);

    InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);

    NMIClass *nc = NMI_CLASS(oc);



    mc->desc = "IBM PowerNV (Non-Virtualized)";

    mc->init = pnv_init;
@@ -1997,6 +2024,7 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data) 
    mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;

    mc->default_ram_id = "pnv.ram";

    ispc->print_info = pnv_pic_print_info;

    nc->nmi_monitor_handler = pnv_nmi;



    object_class_property_add_bool(oc, "hb-mode",

                                   pnv_machine_get_hb, pnv_machine_set_hb,
@@ -2060,6 +2088,7 @@ static const TypeInfo types[] = { 
        .class_size    = sizeof(PnvMachineClass),

        .interfaces = (InterfaceInfo[]) {

            { TYPE_INTERRUPT_STATS_PROVIDER },

            { TYPE_NMI },

            { },

        },

    },

hw/ppc/spapr.c

+11 −18
Original line number Diff line number Diff line
@@ -96,7 +96,6 @@ 
 *

 * We load our kernel at 4M, leaving space for SLOF initial image

 */

#define FDT_MAX_SIZE            0x100000

#define RTAS_MAX_ADDR           0x80000000 /* RTAS must stay below that */

#define FW_MAX_SIZE             0x400000

#define FW_FILE_NAME            "slof.bin"
@@ -1580,9 +1579,7 @@ void spapr_setup_hpt(SpaprMachineState *spapr) 
{

    int hpt_shift;



    if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)

        || (spapr->cas_reboot

            && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {

    if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) {

        hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);

    } else {

        uint64_t current_ram_size;
@@ -1646,16 +1643,10 @@ static void spapr_machine_reset(MachineState *machine) 


    qemu_devices_reset();



    /*

     * If this reset wasn't generated by CAS, we should reset our

     * negotiated options and start from scratch

     */

    if (!spapr->cas_reboot) {

    spapr_ovec_cleanup(spapr->ov5_cas);

    spapr->ov5_cas = spapr_ovec_new();



    ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);

    }



    /*

     * This is fixing some of the default configuration of the XIVE
@@ -1708,8 +1699,6 @@ static void spapr_machine_reset(MachineState *machine) 
    spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0);

    first_ppc_cpu->env.gpr[5] = 0;



    spapr->cas_reboot = false;



    spapr->fwnmi_system_reset_addr = -1;

    spapr->fwnmi_machine_check_addr = -1;

    spapr->fwnmi_machine_check_interlock = -1;
@@ -2837,6 +2826,7 @@ static void spapr_machine_init(MachineState *machine) 
    if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&

        ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,

                              spapr->max_compat_pvr)) {

        spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300);

        /* KVM and TCG always allow GTSE with radix... */

        spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);

    }
@@ -3385,13 +3375,13 @@ static void spapr_machine_finalizefn(Object *obj) 
void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)

{

    SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());

    PowerPCCPU *cpu = POWERPC_CPU(cs);

    CPUPPCState *env = &cpu->env;



    cpu_synchronize_state(cs);

    /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */

    if (spapr->fwnmi_system_reset_addr != -1) {

        uint64_t rtas_addr, addr;

        PowerPCCPU *cpu = POWERPC_CPU(cs);

        CPUPPCState *env = &cpu->env;



        /* get rtas addr from fdt */

        rtas_addr = spapr_get_rtas_addr();
@@ -3405,7 +3395,10 @@ void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 
        stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0);

        env->gpr[3] = addr;

    }

    ppc_cpu_do_system_reset(cs, spapr->fwnmi_system_reset_addr);

    ppc_cpu_do_system_reset(cs);

    if (spapr->fwnmi_system_reset_addr != -1) {

        env->nip = spapr->fwnmi_system_reset_addr;

    }

}



static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)

hw/ppc/spapr_hcall.c

+51 −57
Original line number Diff line number Diff line
@@ -1665,23 +1665,20 @@ static void spapr_handle_transient_dev_before_cas(SpaprMachineState *spapr) 
    spapr_clear_pending_hotplug_events(spapr);

}



static target_ulong h_client_architecture_support(PowerPCCPU *cpu,

target_ulong do_client_architecture_support(PowerPCCPU *cpu,

                                            SpaprMachineState *spapr,

                                                  target_ulong opcode,

                                                  target_ulong *args)

                                            target_ulong vec,

                                            target_ulong fdt_bufsize)

{

    /* Working address in data buffer */

    target_ulong addr = ppc64_phys_to_real(args[0]);

    target_ulong fdt_buf = args[1];

    target_ulong fdt_bufsize = args[2];

    target_ulong ov_table;

    target_ulong ov_table; /* Working address in data buffer */

    uint32_t cas_pvr;

    SpaprOptionVector *ov1_guest, *ov5_guest, *ov5_cas_old;

    SpaprOptionVector *ov1_guest, *ov5_guest;

    bool guest_radix;

    Error *local_err = NULL;

    bool raw_mode_supported = false;

    bool guest_xive;

    CPUState *cs;

    void *fdt;



    /* CAS is supposed to be called early when only the boot vCPU is active. */

    CPU_FOREACH(cs) {
@@ -1694,7 +1691,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 
        }

    }



    cas_pvr = cas_check_pvr(spapr, cpu, &addr, &raw_mode_supported, &local_err);

    cas_pvr = cas_check_pvr(spapr, cpu, &vec, &raw_mode_supported, &local_err);

    if (local_err) {

        error_report_err(local_err);

        return H_HARDWARE;
@@ -1717,7 +1714,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 
    }



    /* For the future use: here @ov_table points to the first option vector */

    ov_table = addr;

    ov_table = vec;



    ov1_guest = spapr_ovec_parse_vector(ov_table, 1);

    if (!ov1_guest) {
@@ -1739,9 +1736,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 
        exit(EXIT_FAILURE);

    }



    /* The radix/hash bit in byte 24 requires special handling: */

    guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300);

    spapr_ovec_clear(ov5_guest, OV5_MMU_RADIX_300);



    guest_xive = spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT);
@@ -1782,30 +1777,16 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 
     * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need

     * to worry about this for now.

     */

    ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas);



    /* also clear the radix/hash bit from the current ov5_cas bits to

     * be in sync with the newly ov5 bits. Else the radix bit will be

     * seen as being removed and this will generate a reset loop

     */

    spapr_ovec_clear(ov5_cas_old, OV5_MMU_RADIX_300);



    /* full range of negotiated ov5 capabilities */

    spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest);

    spapr_ovec_cleanup(ov5_guest);

    /* capabilities that have been added since CAS-generated guest reset.

     * if capabilities have since been removed, generate another reset

     */

    spapr->cas_reboot = !spapr_ovec_subset(ov5_cas_old, spapr->ov5_cas);

    spapr_ovec_cleanup(ov5_cas_old);

    /* Now that processing is finished, set the radix/hash bit for the

     * guest if it requested a valid mode; otherwise terminate the boot. */



    if (guest_radix) {

        if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) {

            error_report("Guest requested unavailable MMU mode (radix).");

            exit(EXIT_FAILURE);

        }

        spapr_ovec_set(spapr->ov5_cas, OV5_MMU_RADIX_300);

    } else {

        if (kvm_enabled() && kvmppc_has_cap_mmu_radix()

            && !kvmppc_has_cap_mmu_hash_v3()) {
@@ -1838,17 +1819,36 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 


    spapr_handle_transient_dev_before_cas(spapr);



    if (!spapr->cas_reboot) {

        void *fdt;

        SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 };



        /* If spapr_machine_reset() did not set up a HPT but one is necessary

         * (because the guest isn't going to use radix) then set it up here. */

    /*

     * If spapr_machine_reset() did not set up a HPT but one is necessary

     * (because the guest isn't going to use radix) then set it up here.

     */

    if ((spapr->patb_entry & PATE1_GR) && !guest_radix) {

        /* legacy hash or new hash: */

        spapr_setup_hpt(spapr);

    }



    fdt = spapr_build_fdt(spapr, false, fdt_bufsize);



    g_free(spapr->fdt_blob);

    spapr->fdt_size = fdt_totalsize(fdt);

    spapr->fdt_initial_size = spapr->fdt_size;

    spapr->fdt_blob = fdt;



    return H_SUCCESS;

}



static target_ulong h_client_architecture_support(PowerPCCPU *cpu,

                                                  SpaprMachineState *spapr,

                                                  target_ulong opcode,

                                                  target_ulong *args)

{

    target_ulong vec = ppc64_phys_to_real(args[0]);

    target_ulong fdt_buf = args[1];

    target_ulong fdt_bufsize = args[2];

    target_ulong ret;

    SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 };



    if (fdt_bufsize < sizeof(hdr)) {

        error_report("SLOF provided insufficient CAS buffer "

                     TARGET_FMT_lu " (min: %zu)", fdt_bufsize, sizeof(hdr));
@@ -1857,25 +1857,19 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 


    fdt_bufsize -= sizeof(hdr);



        fdt = spapr_build_fdt(spapr, false, fdt_bufsize);

        _FDT((fdt_pack(fdt)));



        cpu_physical_memory_write(fdt_buf, &hdr, sizeof(hdr));

        cpu_physical_memory_write(fdt_buf + sizeof(hdr), fdt,

                                  fdt_totalsize(fdt));

        trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));



        g_free(spapr->fdt_blob);

        spapr->fdt_size = fdt_totalsize(fdt);

    ret = do_client_architecture_support(cpu, spapr, vec, fdt_bufsize);

    if (ret == H_SUCCESS) {

        _FDT((fdt_pack(spapr->fdt_blob)));

        spapr->fdt_size = fdt_totalsize(spapr->fdt_blob);

        spapr->fdt_initial_size = spapr->fdt_size;

        spapr->fdt_blob = fdt;

    }



    if (spapr->cas_reboot) {

        qemu_system_reset_request(SHUTDOWN_CAUSE_SUBSYSTEM_RESET);

        cpu_physical_memory_write(fdt_buf, &hdr, sizeof(hdr));

        cpu_physical_memory_write(fdt_buf + sizeof(hdr), spapr->fdt_blob,

                                  spapr->fdt_size);

        trace_spapr_cas_continue(spapr->fdt_size + sizeof(hdr));

    }



    return H_SUCCESS;

    return ret;

}



static target_ulong h_home_node_associativity(PowerPCCPU *cpu,

hw/ppc/spapr_nvdimm.c

+8 −2
Original line number Diff line number Diff line
@@ -37,9 +37,15 @@ void spapr_nvdimm_validate_opts(NVDIMMDevice *nvdimm, uint64_t size, 
    QemuUUID uuid;

    int ret;



    if (object_property_get_int(OBJECT(nvdimm), NVDIMM_LABEL_SIZE_PROP,

                                &error_abort) == 0) {

        error_setg(errp, "PAPR requires NVDIMM devices to have label-size set");

        return;

    }



    if (size % SPAPR_MINIMUM_SCM_BLOCK_SIZE) {

        error_setg(errp, "NVDIMM memory size excluding the label area"

                   " must be a multiple of %" PRIu64 "MB",

        error_setg(errp, "PAPR requires NVDIMM memory size (excluding label)"

                   " to be a multiple of %" PRIu64 "MB",

                   SPAPR_MINIMUM_SCM_BLOCK_SIZE / MiB);

        return;

    }

hw/ppc/spapr_pci.c

+4 −0
Original line number Diff line number Diff line
@@ -1665,6 +1665,10 @@ static void spapr_pci_unplug_request(HotplugHandler *plug_handler, 
            error_setg(errp, "PCI: Hot unplug of PCI bridges not supported");

            return;

        }

        if (object_property_get_uint(OBJECT(pdev), "nvlink2-tgt", NULL)) {

            error_setg(errp, "PCI: Cannot unplug NVLink2 devices");

            return;

        }



        /* ensure any other present functions are pending unplug */

        if (PCI_FUNC(pdev->devfn) == 0) {