Loading target/arm/translate-vfp.inc.c +20 −0 Original line number Diff line number Diff line Loading @@ -1908,3 +1908,23 @@ static bool trans_VNEG_dp(DisasContext *s, arg_VNEG_dp *a) { return do_vfp_2op_dp(s, gen_helper_vfp_negd, a->vd, a->vm); } static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm) { gen_helper_vfp_sqrts(vd, vm, cpu_env); } static bool trans_VSQRT_sp(DisasContext *s, arg_VSQRT_sp *a) { return do_vfp_2op_sp(s, gen_VSQRT_sp, a->vd, a->vm); } static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm) { gen_helper_vfp_sqrtd(vd, vm, cpu_env); } static bool trans_VSQRT_dp(DisasContext *s, arg_VSQRT_dp *a) { return do_vfp_2op_dp(s, gen_VSQRT_dp, a->vd, a->vm); } target/arm/translate.c +1 −13 Original line number Diff line number Diff line Loading @@ -1390,14 +1390,6 @@ static inline void gen_vfp_neg(int dp) gen_helper_vfp_negs(cpu_F0s, cpu_F0s); } static inline void gen_vfp_sqrt(int dp) { if (dp) gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env); else gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env); } static inline void gen_vfp_cmp(int dp) { if (dp) Loading Loading @@ -3098,7 +3090,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) return 1; case 15: switch (rn) { case 1 ... 2: case 1 ... 3: /* Already handled by decodetree */ return 1; default: Loading @@ -3112,7 +3104,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) /* rn is opcode, encoded as per VFP_SREG_N. */ switch (rn) { case 0x00: /* vmov */ case 0x03: /* vsqrt */ break; case 0x04: /* vcvtb.f64.f16, vcvtb.f32.f16 */ Loading Loading @@ -3290,9 +3281,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) case 0: /* cpy */ /* no-op */ break; case 3: /* sqrt */ gen_vfp_sqrt(dp); break; case 4: /* vcvtb.f32.f16, vcvtb.f64.f16 */ { TCGv_ptr fpst = get_fpstatus_ptr(false); Loading target/arm/vfp.decode +5 −0 Original line number Diff line number Diff line Loading @@ -166,3 +166,8 @@ VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... \ vd=%vd_sp vm=%vm_sp VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... \ vd=%vd_dp vm=%vm_dp VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... \ vd=%vd_sp vm=%vm_sp VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... \ vd=%vd_dp vm=%vm_dp Loading
target/arm/translate-vfp.inc.c +20 −0 Original line number Diff line number Diff line Loading @@ -1908,3 +1908,23 @@ static bool trans_VNEG_dp(DisasContext *s, arg_VNEG_dp *a) { return do_vfp_2op_dp(s, gen_helper_vfp_negd, a->vd, a->vm); } static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm) { gen_helper_vfp_sqrts(vd, vm, cpu_env); } static bool trans_VSQRT_sp(DisasContext *s, arg_VSQRT_sp *a) { return do_vfp_2op_sp(s, gen_VSQRT_sp, a->vd, a->vm); } static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm) { gen_helper_vfp_sqrtd(vd, vm, cpu_env); } static bool trans_VSQRT_dp(DisasContext *s, arg_VSQRT_dp *a) { return do_vfp_2op_dp(s, gen_VSQRT_dp, a->vd, a->vm); }
target/arm/translate.c +1 −13 Original line number Diff line number Diff line Loading @@ -1390,14 +1390,6 @@ static inline void gen_vfp_neg(int dp) gen_helper_vfp_negs(cpu_F0s, cpu_F0s); } static inline void gen_vfp_sqrt(int dp) { if (dp) gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env); else gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env); } static inline void gen_vfp_cmp(int dp) { if (dp) Loading Loading @@ -3098,7 +3090,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) return 1; case 15: switch (rn) { case 1 ... 2: case 1 ... 3: /* Already handled by decodetree */ return 1; default: Loading @@ -3112,7 +3104,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) /* rn is opcode, encoded as per VFP_SREG_N. */ switch (rn) { case 0x00: /* vmov */ case 0x03: /* vsqrt */ break; case 0x04: /* vcvtb.f64.f16, vcvtb.f32.f16 */ Loading Loading @@ -3290,9 +3281,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) case 0: /* cpy */ /* no-op */ break; case 3: /* sqrt */ gen_vfp_sqrt(dp); break; case 4: /* vcvtb.f32.f16, vcvtb.f64.f16 */ { TCGv_ptr fpst = get_fpstatus_ptr(false); Loading
target/arm/vfp.decode +5 −0 Original line number Diff line number Diff line Loading @@ -166,3 +166,8 @@ VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... \ vd=%vd_sp vm=%vm_sp VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... \ vd=%vd_dp vm=%vm_dp VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... \ vd=%vd_sp vm=%vm_sp VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... \ vd=%vd_dp vm=%vm_dp