Loading target/arm/translate-vfp.inc.c +10 −0 Original line number Diff line number Diff line Loading @@ -1898,3 +1898,13 @@ static bool trans_VABS_dp(DisasContext *s, arg_VABS_dp *a) { return do_vfp_2op_dp(s, gen_helper_vfp_absd, a->vd, a->vm); } static bool trans_VNEG_sp(DisasContext *s, arg_VNEG_sp *a) { return do_vfp_2op_sp(s, gen_helper_vfp_negs, a->vd, a->vm); } static bool trans_VNEG_dp(DisasContext *s, arg_VNEG_dp *a) { return do_vfp_2op_dp(s, gen_helper_vfp_negd, a->vd, a->vm); } target/arm/translate.c +1 −5 Original line number Diff line number Diff line Loading @@ -3098,7 +3098,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) return 1; case 15: switch (rn) { case 1: case 1 ... 2: /* Already handled by decodetree */ return 1; default: Loading @@ -3112,7 +3112,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) /* rn is opcode, encoded as per VFP_SREG_N. */ switch (rn) { case 0x00: /* vmov */ case 0x02: /* vneg */ case 0x03: /* vsqrt */ break; Loading Loading @@ -3291,9 +3290,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) case 0: /* cpy */ /* no-op */ break; case 2: /* neg */ gen_vfp_neg(dp); break; case 3: /* sqrt */ gen_vfp_sqrt(dp); break; Loading target/arm/vfp.decode +5 −0 Original line number Diff line number Diff line Loading @@ -161,3 +161,8 @@ VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... \ vd=%vd_sp vm=%vm_sp VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... \ vd=%vd_dp vm=%vm_dp VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... \ vd=%vd_sp vm=%vm_sp VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... \ vd=%vd_dp vm=%vm_dp Loading
target/arm/translate-vfp.inc.c +10 −0 Original line number Diff line number Diff line Loading @@ -1898,3 +1898,13 @@ static bool trans_VABS_dp(DisasContext *s, arg_VABS_dp *a) { return do_vfp_2op_dp(s, gen_helper_vfp_absd, a->vd, a->vm); } static bool trans_VNEG_sp(DisasContext *s, arg_VNEG_sp *a) { return do_vfp_2op_sp(s, gen_helper_vfp_negs, a->vd, a->vm); } static bool trans_VNEG_dp(DisasContext *s, arg_VNEG_dp *a) { return do_vfp_2op_dp(s, gen_helper_vfp_negd, a->vd, a->vm); }
target/arm/translate.c +1 −5 Original line number Diff line number Diff line Loading @@ -3098,7 +3098,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) return 1; case 15: switch (rn) { case 1: case 1 ... 2: /* Already handled by decodetree */ return 1; default: Loading @@ -3112,7 +3112,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) /* rn is opcode, encoded as per VFP_SREG_N. */ switch (rn) { case 0x00: /* vmov */ case 0x02: /* vneg */ case 0x03: /* vsqrt */ break; Loading Loading @@ -3291,9 +3290,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) case 0: /* cpy */ /* no-op */ break; case 2: /* neg */ gen_vfp_neg(dp); break; case 3: /* sqrt */ gen_vfp_sqrt(dp); break; Loading
target/arm/vfp.decode +5 −0 Original line number Diff line number Diff line Loading @@ -161,3 +161,8 @@ VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... \ vd=%vd_sp vm=%vm_sp VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... \ vd=%vd_dp vm=%vm_dp VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... \ vd=%vd_sp vm=%vm_sp VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... \ vd=%vd_dp vm=%vm_dp