Commit b4dd99a3 authored by Petar Jovanovic's avatar Petar Jovanovic
Browse files

target-mips: add support for CP0_Config5 



Add CP0_Config5, define rw_bitmask and enable modifications.

Signed-off-by: default avatarPetar Jovanovic <petar.jovanovic@imgtec.com>
Reviewed-by: default avatarEric Johnson <eric.johnson@imgtec.com>
parent b4160af1

target-mips/cpu.h

+10 −0
Original line number Diff line number Diff line
@@ -73,6 +73,7 @@ struct CPUMIPSFPUContext { 
    float_status fp_status;

    /* fpu implementation/revision register (fir) */

    uint32_t fcr0;

#define FCR0_UFRP 28

#define FCR0_F64 22

#define FCR0_L 21

#define FCR0_W 20
@@ -371,6 +372,15 @@ struct CPUMIPSState { 
    uint32_t CP0_Config4;

    uint32_t CP0_Config4_rw_bitmask;

#define CP0C4_M    31

    uint32_t CP0_Config5;

    uint32_t CP0_Config5_rw_bitmask;

#define CP0C5_M          31

#define CP0C5_K          30

#define CP0C5_CV         29

#define CP0C5_EVA        28

#define CP0C5_MSAEn      27

#define CP0C5_UFR        2

#define CP0C5_NFExists   0

    int32_t CP0_Config6;

    int32_t CP0_Config7;

    /* XXX: Maybe make LLAddr per-TC? */

target-mips/helper.h

+1 −0
Original line number Diff line number Diff line
@@ -135,6 +135,7 @@ DEF_HELPER_2(mttc0_ebase, void, env, tl) 
DEF_HELPER_2(mtc0_config0, void, env, tl)

DEF_HELPER_2(mtc0_config2, void, env, tl)

DEF_HELPER_2(mtc0_config4, void, env, tl)

DEF_HELPER_2(mtc0_config5, void, env, tl)

DEF_HELPER_2(mtc0_lladdr, void, env, tl)

DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32)

DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32)

target-mips/op_helper.c

+6 −0
Original line number Diff line number Diff line
@@ -1495,6 +1495,12 @@ void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1) 
                       (arg1 & env->CP0_Config4_rw_bitmask);

}



void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)

{

    env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |

                       (arg1 & env->CP0_Config5_rw_bitmask);

}



void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)

{

    target_long mask = env->CP0_LLAddr_rw_bitmask;

target-mips/translate.c

+12 −2
Original line number Diff line number Diff line
@@ -4409,7 +4409,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) 
            gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));

            rn = "Config4";

            break;

        /* 5 is reserved */

        case 5:

            gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));

            rn = "Config5";

            break;

        /* 6,7 are implementation dependent */

        case 6:

            gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
@@ -4991,7 +4994,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) 
            rn = "Config4";

            ctx->bstate = BS_STOP;

            break;

        /* 5 is reserved */

        case 5:

            gen_helper_mtc0_config5(cpu_env, arg);

            rn = "Config5";

            /* Stop translation as we may have switched the execution mode */

            ctx->bstate = BS_STOP;

            break;

        /* 6,7 are implementation dependent */

        case 6:

            /* ignored */
@@ -15927,6 +15935,8 @@ void cpu_state_reset(CPUMIPSState *env) 
    env->CP0_Config3 = env->cpu_model->CP0_Config3;

    env->CP0_Config4 = env->cpu_model->CP0_Config4;

    env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;

    env->CP0_Config5 = env->cpu_model->CP0_Config5;

    env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;

    env->CP0_Config6 = env->cpu_model->CP0_Config6;

    env->CP0_Config7 = env->cpu_model->CP0_Config7;

    env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask

target-mips/translate_init.c

+11 −1
Original line number Diff line number Diff line
@@ -48,6 +48,9 @@ 
#define MIPS_CONFIG4                                              \

((0 << CP0C4_M))



#define MIPS_CONFIG5                                              \

((0 << CP0C5_M))



/* MMU types, the first four entries have the same layout as the

   CP0C0_MT field.  */

enum mips_mmu_types {
@@ -69,6 +72,8 @@ struct mips_def_t { 
    int32_t CP0_Config3;

    int32_t CP0_Config4;

    int32_t CP0_Config4_rw_bitmask;

    int32_t CP0_Config5;

    int32_t CP0_Config5_rw_bitmask;

    int32_t CP0_Config6;

    int32_t CP0_Config7;

    target_ulong CP0_LLAddr_rw_bitmask;
@@ -351,8 +356,13 @@ static const mips_def_t mips_defs[] = 
                       (1 << CP0C1_CA),

        .CP0_Config2 = MIPS_CONFIG2,

        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_M),

        .CP0_Config4 = MIPS_CONFIG4,

        .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),

        .CP0_Config4_rw_bitmask = 0,

        .CP0_Config5 = MIPS_CONFIG5,

        .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) |

                                  (1 << CP0C5_CV) | (0 << CP0C5_EVA) |

                                  (1 << CP0C5_MSAEn) | (0 << CP0C5_UFR) |

                                  (0 << CP0C5_NFExists),

        .CP0_LLAddr_rw_bitmask = 0,

        .CP0_LLAddr_shift = 4,

        .SYNCI_Step = 32,