Commit b4160af1 authored by Petar Jovanovic's avatar Petar Jovanovic
Browse files

target-mips: add support for CP0_Config4 



Add CP0_Config4, define rw_bitmask.

Signed-off-by: default avatarPetar Jovanovic <petar.jovanovic@imgtec.com>
Reviewed-by: default avatarEric Johnson <eric.johnson@imgtec.com>
parent e527526d

target-mips/cpu.h

+3 −0
Original line number Diff line number Diff line
@@ -368,6 +368,9 @@ struct CPUMIPSState { 
#define CP0C3_MT   2

#define CP0C3_SM   1

#define CP0C3_TL   0

    uint32_t CP0_Config4;

    uint32_t CP0_Config4_rw_bitmask;

#define CP0C4_M    31

    int32_t CP0_Config6;

    int32_t CP0_Config7;

    /* XXX: Maybe make LLAddr per-TC? */

target-mips/helper.h

+1 −0
Original line number Diff line number Diff line
@@ -134,6 +134,7 @@ DEF_HELPER_2(mtc0_ebase, void, env, tl) 
DEF_HELPER_2(mttc0_ebase, void, env, tl)

DEF_HELPER_2(mtc0_config0, void, env, tl)

DEF_HELPER_2(mtc0_config2, void, env, tl)

DEF_HELPER_2(mtc0_config4, void, env, tl)

DEF_HELPER_2(mtc0_lladdr, void, env, tl)

DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32)

DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32)

target-mips/op_helper.c

+6 −0
Original line number Diff line number Diff line
@@ -1489,6 +1489,12 @@ void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1) 
    env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);

}



void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)

{

    env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |

                       (arg1 & env->CP0_Config4_rw_bitmask);

}



void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)

{

    target_long mask = env->CP0_LLAddr_rw_bitmask;

target-mips/translate.c

+13 −2
Original line number Diff line number Diff line
@@ -4405,7 +4405,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) 
            gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));

            rn = "Config3";

            break;

        /* 4,5 are reserved */

        case 4:

            gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));

            rn = "Config4";

            break;

        /* 5 is reserved */

        /* 6,7 are implementation dependent */

        case 6:

            gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
@@ -4982,7 +4986,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) 
            /* ignored, read only */

            rn = "Config3";

            break;

        /* 4,5 are reserved */

        case 4:

            gen_helper_mtc0_config4(cpu_env, arg);

            rn = "Config4";

            ctx->bstate = BS_STOP;

            break;

        /* 5 is reserved */

        /* 6,7 are implementation dependent */

        case 6:

            /* ignored */
@@ -15916,6 +15925,8 @@ void cpu_state_reset(CPUMIPSState *env) 
    env->CP0_Config1 = env->cpu_model->CP0_Config1;

    env->CP0_Config2 = env->cpu_model->CP0_Config2;

    env->CP0_Config3 = env->cpu_model->CP0_Config3;

    env->CP0_Config4 = env->cpu_model->CP0_Config4;

    env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;

    env->CP0_Config6 = env->cpu_model->CP0_Config6;

    env->CP0_Config7 = env->cpu_model->CP0_Config7;

    env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask

target-mips/translate_init.c

+8 −1
Original line number Diff line number Diff line
@@ -45,6 +45,9 @@ 
 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) |        \

 (0 << CP0C3_SM) | (0 << CP0C3_TL))



#define MIPS_CONFIG4                                              \

((0 << CP0C4_M))



/* MMU types, the first four entries have the same layout as the

   CP0C0_MT field.  */

enum mips_mmu_types {
@@ -64,6 +67,8 @@ struct mips_def_t { 
    int32_t CP0_Config1;

    int32_t CP0_Config2;

    int32_t CP0_Config3;

    int32_t CP0_Config4;

    int32_t CP0_Config4_rw_bitmask;

    int32_t CP0_Config6;

    int32_t CP0_Config7;

    target_ulong CP0_LLAddr_rw_bitmask;
@@ -345,7 +350,9 @@ static const mips_def_t mips_defs[] = 
                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |

                       (1 << CP0C1_CA),

        .CP0_Config2 = MIPS_CONFIG2,

        .CP0_Config3 = MIPS_CONFIG3,

        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_M),

        .CP0_Config4 = MIPS_CONFIG4,

        .CP0_Config4_rw_bitmask = 0,

        .CP0_LLAddr_rw_bitmask = 0,

        .CP0_LLAddr_shift = 4,

        .SYNCI_Step = 32,