Commit b48ff240 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Implement SVE vector splice (predicated) 



Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180613015641.5667-10-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent dae8fb90

target/arm/helper-sve.h

+2 −0
Original line number Diff line number Diff line
@@ -479,6 +479,8 @@ DEF_HELPER_FLAGS_4(sve_rbit_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) 
DEF_HELPER_FLAGS_4(sve_rbit_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(sve_rbit_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_5(sve_splice, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)

target/arm/sve.decode

+3 −0
Original line number Diff line number Diff line
@@ -463,6 +463,9 @@ REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn 
REVW            00000101 .. 1001 10 100 ... ..... .....         @rd_pg_rn

RBIT            00000101 .. 1001 11 100 ... ..... .....         @rd_pg_rn



# SVE vector splice (predicated)

SPLICE          00000101 .. 101 100 100 ... ..... .....         @rdn_pg_rm



### SVE Predicate Logical Operations Group



# SVE predicate logical operations

target/arm/sve_helper.c

+37 −0
Original line number Diff line number Diff line
@@ -2109,3 +2109,40 @@ int32_t HELPER(sve_last_active_element)(void *vg, uint32_t pred_desc) 


    return last_active_element(vg, DIV_ROUND_UP(oprsz, 8), esz);

}



void HELPER(sve_splice)(void *vd, void *vn, void *vm, void *vg, uint32_t desc)

{

    intptr_t opr_sz = simd_oprsz(desc) / 8;

    int esz = simd_data(desc);

    uint64_t pg, first_g, last_g, len, mask = pred_esz_masks[esz];

    intptr_t i, first_i, last_i;

    ARMVectorReg tmp;



    first_i = last_i = 0;

    first_g = last_g = 0;



    /* Find the extent of the active elements within VG.  */

    for (i = QEMU_ALIGN_UP(opr_sz, 8) - 8; i >= 0; i -= 8) {

        pg = *(uint64_t *)(vg + i) & mask;

        if (pg) {

            if (last_g == 0) {

                last_g = pg;

                last_i = i;

            }

            first_g = pg;

            first_i = i;

        }

    }



    len = 0;

    if (first_g != 0) {

        first_i = first_i * 8 + ctz64(first_g);

        last_i = last_i * 8 + 63 - clz64(last_g);

        len = last_i - first_i + (1 << esz);

        if (vd == vm) {

            vm = memcpy(&tmp, vm, opr_sz * 8);

        }

        swap_memmove(vd, vn + first_i, len);

    }

    swap_memmove(vd + len, vm, opr_sz * 8 - len);

}

target/arm/translate-sve.c

+13 −0
Original line number Diff line number Diff line
@@ -2681,6 +2681,19 @@ static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a, uint32_t insn) 
    return do_zpz_ool(s, a, fns[a->esz]);

}



static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a, uint32_t insn)

{

    if (sve_access_check(s)) {

        unsigned vsz = vec_full_reg_size(s);

        tcg_gen_gvec_4_ool(vec_full_reg_offset(s, a->rd),

                           vec_full_reg_offset(s, a->rn),

                           vec_full_reg_offset(s, a->rm),

                           pred_full_reg_offset(s, a->pg),

                           vsz, vsz, a->esz, gen_helper_sve_splice);

    }

    return true;

}



/*

 *** SVE Memory - 32-bit Gather and Unsized Contiguous Group

 */