Commit ab978335 authored by Peter Maydell's avatar Peter Maydell
Browse files

target/arm: Convert Neon VPMIN/VPMAX/VPADD float 3-reg-same insns to decodetree 



Convert the Neon float VPMIN, VPMAX and VPADD 3-reg-same insns to
decodetree. These are the only remaining 'pairwise' operations,
so we can delete the pairwise-specific bits of the old decoder's
for-each-element loop now.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20200512163904.10918-13-peter.maydell@linaro.org
parent a26a352b

target/arm/neon-dp.decode

+5 −0
Original line number Diff line number Diff line
@@ -48,6 +48,8 @@ 
# For FP insns the high bit of 'size' is used as part of opcode decode

@3same_fp        .... ... . . . . size:1 .... .... .... . q:1 . . .... \

                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp

@3same_fp_q0     .... ... . . . . size:1 .... .... .... . 0 . . .... \

                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0



VHADD_S_3s       1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same

VHADD_U_3s       1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same
@@ -176,4 +178,7 @@ VQRDMLSH_3s 1111 001 1 0 . .. .... .... 1100 ... 1 .... @3same 


VADD_fp_3s       1111 001 0 0 . 0 . .... .... 1101 ... 0 .... @3same_fp

VSUB_fp_3s       1111 001 0 0 . 1 . .... .... 1101 ... 0 .... @3same_fp

VPADD_fp_3s      1111 001 1 0 . 0 . .... .... 1101 ... 0 .... @3same_fp_q0

VABD_fp_3s       1111 001 1 0 . 1 . .... .... 1101 ... 0 .... @3same_fp

VPMAX_fp_3s      1111 001 1 0 . 0 . .... .... 1111 ... 0 .... @3same_fp_q0

VPMIN_fp_3s      1111 001 1 0 . 1 . .... .... 1111 ... 0 .... @3same_fp_q0

target/arm/translate-neon.inc.c

+63 −0
Original line number Diff line number Diff line
@@ -1049,3 +1049,66 @@ DO_3SAME_VQDMULH(VQRDMULH, qrdmulh) 
DO_3S_FP_GVEC(VADD, gen_helper_gvec_fadd_s)

DO_3S_FP_GVEC(VSUB, gen_helper_gvec_fsub_s)

DO_3S_FP_GVEC(VABD, gen_helper_gvec_fabd_s)



static bool do_3same_fp_pair(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn)

{

    /* FP operations handled pairwise 32 bits at a time */

    TCGv_i32 tmp, tmp2, tmp3;

    TCGv_ptr fpstatus;



    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {

        return false;

    }



    /* UNDEF accesses to D16-D31 if they don't exist. */

    if (!dc_isar_feature(aa32_simd_r32, s) &&

        ((a->vd | a->vn | a->vm) & 0x10)) {

        return false;

    }



    if (!vfp_access_check(s)) {

        return true;

    }



    assert(a->q == 0); /* enforced by decode patterns */



    /*

     * Note that we have to be careful not to clobber the source operands

     * in the "vm == vd" case by storing the result of the first pass too

     * early. Since Q is 0 there are always just two passes, so instead

     * of a complicated loop over each pass we just unroll.

     */

    fpstatus = get_fpstatus_ptr(1);

    tmp = neon_load_reg(a->vn, 0);

    tmp2 = neon_load_reg(a->vn, 1);

    fn(tmp, tmp, tmp2, fpstatus);

    tcg_temp_free_i32(tmp2);



    tmp3 = neon_load_reg(a->vm, 0);

    tmp2 = neon_load_reg(a->vm, 1);

    fn(tmp3, tmp3, tmp2, fpstatus);

    tcg_temp_free_i32(tmp2);

    tcg_temp_free_ptr(fpstatus);



    neon_store_reg(a->vd, 0, tmp);

    neon_store_reg(a->vd, 1, tmp3);

    return true;

}



/*

 * For all the functions using this macro, size == 1 means fp16,

 * which is an architecture extension we don't implement yet.

 */

#define DO_3S_FP_PAIR(INSN,FUNC)                                    \

    static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \

    {                                                               \

        if (a->size != 0) {                                         \

            /* TODO fp16 support */                                 \

            return false;                                           \

        }                                                           \

        return do_3same_fp_pair(s, a, FUNC);                        \

    }



DO_3S_FP_PAIR(VPADD, gen_helper_vfp_adds)

DO_3S_FP_PAIR(VPMAX, gen_helper_vfp_maxs)

DO_3S_FP_PAIR(VPMIN, gen_helper_vfp_mins)

target/arm/translate.c

+8 −55
Original line number Diff line number Diff line
@@ -5348,7 +5348,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) 
    int shift;

    int pass;

    int count;

    int pairwise;

    int u;

    int vec_size;

    uint32_t imm;
@@ -5433,6 +5432,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) 
        case NEON_3R_VPMIN:

        case NEON_3R_VPADD_VQRDMLAH:

        case NEON_3R_VQDMULH_VQRDMULH:

        case NEON_3R_FLOAT_ARITH:

            /* Already handled by decodetree */

            return 1;

        }
@@ -5441,16 +5441,11 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) 
            /* 64-bit element instructions: handled by decodetree */

            return 1;

        }

        pairwise = 0;

        switch (op) {

        case NEON_3R_FLOAT_ARITH:

            pairwise = (u && size < 2); /* if VPADD (float) */

            if (!pairwise) {

                return 1; /* handled by decodetree */

            }

            break;

        case NEON_3R_FLOAT_MINMAX:

            pairwise = u; /* if VPMIN/VPMAX (float) */

            if (u) {

                return 1; /* VPMIN/VPMAX handled by decodetree */

            }

            break;

        case NEON_3R_FLOAT_CMP:

            if (!u && size) {
@@ -5478,41 +5473,12 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) 
            break;

        }



        if (pairwise && q) {

            /* All the pairwise insns UNDEF if Q is set */

            return 1;

        }



        for (pass = 0; pass < (q ? 4 : 2); pass++) {



        if (pairwise) {

            /* Pairwise.  */

            if (pass < 1) {

                tmp = neon_load_reg(rn, 0);

                tmp2 = neon_load_reg(rn, 1);

            } else {

                tmp = neon_load_reg(rm, 0);

                tmp2 = neon_load_reg(rm, 1);

            }

        } else {

        /* Elementwise.  */

        tmp = neon_load_reg(rn, pass);

        tmp2 = neon_load_reg(rm, pass);

        }

        switch (op) {

        case NEON_3R_FLOAT_ARITH: /* Floating point arithmetic. */

        {

            TCGv_ptr fpstatus = get_fpstatus_ptr(1);

            switch ((u << 2) | size) {

            case 4: /* VPADD */

                gen_helper_vfp_adds(tmp, tmp, tmp2, fpstatus);

                break;

            default:

                abort();

            }

            tcg_temp_free_ptr(fpstatus);

            break;

        }

        case NEON_3R_FLOAT_MULTIPLY:

        {

            TCGv_ptr fpstatus = get_fpstatus_ptr(1);
@@ -5603,22 +5569,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) 
        }

        tcg_temp_free_i32(tmp2);



        /* Save the result.  For elementwise operations we can put it

           straight into the destination register.  For pairwise operations

           we have to be careful to avoid clobbering the source operands.  */

        if (pairwise && rd == rm) {

            neon_store_scratch(pass, tmp);

        } else {

        neon_store_reg(rd, pass, tmp);

        }



        } /* for pass */

        if (pairwise && rd == rm) {

            for (pass = 0; pass < (q ? 4 : 2); pass++) {

                tmp = neon_load_scratch(pass);

                neon_store_reg(rd, pass, tmp);

            }

        }

        /* End of 3 register same size operations.  */

    } else if (insn & (1 << 4)) {

        if ((insn & 0x00380080) != 0) {