Commit a26a352b authored by Peter Maydell's avatar Peter Maydell
Browse files

target/arm: Convert Neon VADD, VSUB, VABD 3-reg-same insns to decodetree 



Convert the Neon VADD, VSUB, VABD 3-reg-same insns to decodetree.
We already have gvec helpers for addition and subtraction, but must
add one for fabd.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20200512163904.10918-12-peter.maydell@linaro.org
parent 7ecc28bc

target/arm/helper.h

+2 −1
Original line number Diff line number Diff line
@@ -396,7 +396,6 @@ DEF_HELPER_FLAGS_2(neon_qneg_s16, TCG_CALL_NO_RWG, i32, env, i32) 
DEF_HELPER_FLAGS_2(neon_qneg_s32, TCG_CALL_NO_RWG, i32, env, i32)

DEF_HELPER_FLAGS_2(neon_qneg_s64, TCG_CALL_NO_RWG, i64, env, i64)



DEF_HELPER_3(neon_abd_f32, i32, i32, i32, ptr)

DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, ptr)

DEF_HELPER_3(neon_cge_f32, i32, i32, i32, ptr)

DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, ptr)
@@ -595,6 +594,8 @@ DEF_HELPER_FLAGS_5(gvec_fmul_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) 
DEF_HELPER_FLAGS_5(gvec_fmul_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(gvec_fmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_5(gvec_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_5(gvec_ftsmul_h, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(gvec_ftsmul_s, TCG_CALL_NO_RWG,

target/arm/neon-dp.decode

+8 −0
Original line number Diff line number Diff line
@@ -45,6 +45,10 @@ 
@3same_q0        .... ... . . . size:2 .... .... .... . 0 . . .... \

                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0



# For FP insns the high bit of 'size' is used as part of opcode decode

@3same_fp        .... ... . . . . size:1 .... .... .... . q:1 . . .... \

                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp



VHADD_S_3s       1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same

VHADD_U_3s       1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same

VQADD_S_3s       1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
@@ -169,3 +173,7 @@ SHA256SU1_3s 1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... \ 
                 vm=%vm_dp vn=%vn_dp vd=%vd_dp



VQRDMLSH_3s      1111 001 1 0 . .. .... .... 1100 ... 1 .... @3same



VADD_fp_3s       1111 001 0 0 . 0 . .... .... 1101 ... 0 .... @3same_fp

VSUB_fp_3s       1111 001 0 0 . 1 . .... .... 1101 ... 0 .... @3same_fp

VABD_fp_3s       1111 001 1 0 . 1 . .... .... 1101 ... 0 .... @3same_fp

target/arm/neon_helper.c

+0 −7
Original line number Diff line number Diff line
@@ -1825,13 +1825,6 @@ uint64_t HELPER(neon_qneg_s64)(CPUARMState *env, uint64_t x) 
}



/* NEON Float helpers.  */

uint32_t HELPER(neon_abd_f32)(uint32_t a, uint32_t b, void *fpstp)

{

    float_status *fpst = fpstp;

    float32 f0 = make_float32(a);

    float32 f1 = make_float32(b);

    return float32_val(float32_abs(float32_sub(f0, f1, fpst)));

}



/* Floating point comparisons produce an integer result.

 * Note that EQ doesn't signal InvalidOp for QNaNs but GE and GT do.

target/arm/translate-neon.inc.c

+28 −0
Original line number Diff line number Diff line
@@ -1021,3 +1021,31 @@ DO_3SAME_PAIR(VPADD, padd_u) 


DO_3SAME_VQDMULH(VQDMULH, qdmulh)

DO_3SAME_VQDMULH(VQRDMULH, qrdmulh)



/*

 * For all the functions using this macro, size == 1 means fp16,

 * which is an architecture extension we don't implement yet.

 */

#define DO_3S_FP_GVEC(INSN,FUNC)                                        \

    static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \

                                uint32_t rn_ofs, uint32_t rm_ofs,       \

                                uint32_t oprsz, uint32_t maxsz)         \

    {                                                                   \

        TCGv_ptr fpst = get_fpstatus_ptr(1);                            \

        tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpst,                \

                           oprsz, maxsz, 0, FUNC);                      \

        tcg_temp_free_ptr(fpst);                                        \

    }                                                                   \

    static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a)     \

    {                                                                   \

        if (a->size != 0) {                                             \

            /* TODO fp16 support */                                     \

            return false;                                               \

        }                                                               \

        return do_3same(s, a, gen_##INSN##_3s);                         \

    }





DO_3S_FP_GVEC(VADD, gen_helper_gvec_fadd_s)

DO_3S_FP_GVEC(VSUB, gen_helper_gvec_fsub_s)

DO_3S_FP_GVEC(VABD, gen_helper_gvec_fabd_s)

target/arm/translate.c

+3 −7
Original line number Diff line number Diff line
@@ -5445,6 +5445,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) 
        switch (op) {

        case NEON_3R_FLOAT_ARITH:

            pairwise = (u && size < 2); /* if VPADD (float) */

            if (!pairwise) {

                return 1; /* handled by decodetree */

            }

            break;

        case NEON_3R_FLOAT_MINMAX:

            pairwise = u; /* if VPMIN/VPMAX (float) */
@@ -5501,16 +5504,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) 
        {

            TCGv_ptr fpstatus = get_fpstatus_ptr(1);

            switch ((u << 2) | size) {

            case 0: /* VADD */

            case 4: /* VPADD */

                gen_helper_vfp_adds(tmp, tmp, tmp2, fpstatus);

                break;

            case 2: /* VSUB */

                gen_helper_vfp_subs(tmp, tmp, tmp2, fpstatus);

                break;

            case 6: /* VABD */

                gen_helper_neon_abd_f32(tmp, tmp, tmp2, fpstatus);

                break;

            default:

                abort();

            }