Commit a9bd9b5a authored by Leon Alrae's avatar Leon Alrae
Browse files

hw/mips/cps: create GCR block inside CPS 



Signed-off-by: default avatarLeon Alrae <leon.alrae@imgtec.com>
parent 3994215d

hw/mips/cps.c

+23 −0
Original line number Diff line number Diff line
@@ -62,6 +62,8 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) 
    CPUMIPSState *env;

    MIPSCPU *cpu;

    int i;

    Error *err = NULL;

    target_ulong gcr_base;



    for (i = 0; i < s->num_vp; i++) {

        cpu = cpu_mips_init(s->cpu_model);
@@ -76,6 +78,27 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) 
        cpu_mips_clock_init(env);

        qemu_register_reset(main_cpu_reset, cpu);

    }



    cpu = MIPS_CPU(first_cpu);

    env = &cpu->env;



    /* Global Configuration Registers */

    gcr_base = env->CP0_CMGCRBase << 4;



    object_initialize(&s->gcr, sizeof(s->gcr), TYPE_MIPS_GCR);

    qdev_set_parent_bus(DEVICE(&s->gcr), sysbus_get_default());



    object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err);

    object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err);

    object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err);

    object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err);

    if (err != NULL) {

        error_propagate(errp, err);

        return;

    }



    memory_region_add_subregion(&s->container, gcr_base,

                            sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0));

}



static Property mips_cps_properties[] = {

include/hw/mips/cps.h

+2 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#define MIPS_CPS_H



#include "hw/sysbus.h"

#include "hw/misc/mips_cmgcr.h"



#define TYPE_MIPS_CPS "mips-cps"

#define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS)
@@ -33,6 +34,7 @@ typedef struct MIPSCPSState { 
    char *cpu_model;



    MemoryRegion container;

    MIPSGCRState gcr;

} MIPSCPSState;



qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number);