Commit 3994215d authored by Yongbok Kim's avatar Yongbok Kim Committed by Leon Alrae
Browse files

hw/mips: add initial Global Config Register support 



Add initial GCR support to indicate number of VPs present in the system,
L2 bypass mode and revision number.

Signed-off-by: default avatarYongbok Kim <yongbok.kim@imgtec.com>
[leon.alrae@imgtec.com:
 * removed GIC part,
 * changed commit message,
 * replaced %lx format spec. with PRIx64,
 * renamed mips_gcr.{c,h} to mips_cmgcr.{c,h},
 * replaced CONFIG_MIPS_GIC with CONFIG_MIPS_CPS]
Signed-off-by: default avatarLeon Alrae <leon.alrae@imgtec.com>
parent c870e3f5

hw/misc/Makefile.objs

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@@ -43,6 +43,7 @@ obj-$(CONFIG_SLAVIO) += slavio_misc.o 
obj-$(CONFIG_ZYNQ) += zynq_slcr.o

obj-$(CONFIG_ZYNQ) += zynq-xadc.o

obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o

obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o



obj-$(CONFIG_PVPANIC) += pvpanic.o

obj-$(CONFIG_EDU) += edu.o

hw/misc/mips_cmgcr.c

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/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.

 * Authors: Sanjay Lal <sanjayl@kymasys.com>

 *

 * Copyright (C) 2015 Imagination Technologies

 */



#include "qemu/osdep.h"

#include "qapi/error.h"

#include "hw/hw.h"

#include "hw/sysbus.h"

#include "sysemu/sysemu.h"

#include "hw/misc/mips_cmgcr.h"



/* Read GCR registers */

static uint64_t gcr_read(void *opaque, hwaddr addr, unsigned size)

{

    MIPSGCRState *gcr = (MIPSGCRState *) opaque;



    switch (addr) {

    /* Global Control Block Register */

    case GCR_CONFIG_OFS:

        /* Set PCORES to 0 */

        return 0;

    case GCR_BASE_OFS:

        return gcr->gcr_base;

    case GCR_REV_OFS:

        return gcr->gcr_rev;

    case GCR_L2_CONFIG_OFS:

        /* L2 BYPASS */

        return GCR_L2_CONFIG_BYPASS_MSK;

        /* Core-Local and Core-Other Control Blocks */

    case MIPS_CLCB_OFS + GCR_CL_CONFIG_OFS:

    case MIPS_COCB_OFS + GCR_CL_CONFIG_OFS:

        /* Set PVP to # of VPs - 1 */

        return gcr->num_vps - 1;

    case MIPS_CLCB_OFS + GCR_CL_OTHER_OFS:

        return 0;

    default:

        qemu_log_mask(LOG_UNIMP, "Read %d bytes at GCR offset 0x%" HWADDR_PRIx

                      "\n", size, addr);

        return 0;

    }

    return 0;

}



/* Write GCR registers */

static void gcr_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)

{

    switch (addr) {

    default:

        qemu_log_mask(LOG_UNIMP, "Write %d bytes at GCR offset 0x%" HWADDR_PRIx

                      " 0x%" PRIx64 "\n", size, addr, data);

        break;

    }

}



static const MemoryRegionOps gcr_ops = {

    .read = gcr_read,

    .write = gcr_write,

    .endianness = DEVICE_NATIVE_ENDIAN,

    .impl = {

        .max_access_size = 8,

    },

};



static void mips_gcr_init(Object *obj)

{

    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

    MIPSGCRState *s = MIPS_GCR(obj);



    memory_region_init_io(&s->iomem, OBJECT(s), &gcr_ops, s,

                          "mips-gcr", GCR_ADDRSPACE_SZ);

    sysbus_init_mmio(sbd, &s->iomem);

}



static Property mips_gcr_properties[] = {

    DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1),

    DEFINE_PROP_INT32("gcr-rev", MIPSGCRState, gcr_rev, 0x800),

    DEFINE_PROP_UINT64("gcr-base", MIPSGCRState, gcr_base, GCR_BASE_ADDR),

    DEFINE_PROP_END_OF_LIST(),

};



static void mips_gcr_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->props = mips_gcr_properties;

}



static const TypeInfo mips_gcr_info = {

    .name          = TYPE_MIPS_GCR,

    .parent        = TYPE_SYS_BUS_DEVICE,

    .instance_size = sizeof(MIPSGCRState),

    .instance_init = mips_gcr_init,

    .class_init    = mips_gcr_class_init,

};



static void mips_gcr_register_types(void)

{

    type_register_static(&mips_gcr_info);

}



type_init(mips_gcr_register_types)

include/hw/misc/mips_cmgcr.h

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/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2015 Imagination Technologies

 *

 */



#ifndef _MIPS_GCR_H

#define _MIPS_GCR_H



#define TYPE_MIPS_GCR "mips-gcr"

#define MIPS_GCR(obj) OBJECT_CHECK(MIPSGCRState, (obj), TYPE_MIPS_GCR)



#define GCR_BASE_ADDR           0x1fbf8000ULL

#define GCR_ADDRSPACE_SZ        0x8000



/* Offsets to register blocks */

#define MIPS_GCB_OFS        0x0000 /* Global Control Block */

#define MIPS_CLCB_OFS       0x2000 /* Core Local Control Block */

#define MIPS_COCB_OFS       0x4000 /* Core Other Control Block */

#define MIPS_GDB_OFS        0x6000 /* Global Debug Block */



/* Global Control Block Register Map */

#define GCR_CONFIG_OFS      0x0000

#define GCR_BASE_OFS        0x0008

#define GCR_REV_OFS         0x0030

#define GCR_L2_CONFIG_OFS   0x0130



/* Core Local and Core Other Block Register Map */

#define GCR_CL_CONFIG_OFS   0x0010

#define GCR_CL_OTHER_OFS    0x0018



/* GCR_L2_CONFIG register fields */

#define GCR_L2_CONFIG_BYPASS_SHF    20

#define GCR_L2_CONFIG_BYPASS_MSK    ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF)



typedef struct MIPSGCRState MIPSGCRState;

struct MIPSGCRState {

    SysBusDevice parent_obj;



    int32_t gcr_rev;

    int32_t num_vps;

    hwaddr gcr_base;

    MemoryRegion iomem;

};



#endif /* _MIPS_GCR_H */