Commit c870e3f5 authored by Yongbok Kim's avatar Yongbok Kim Committed by Leon Alrae
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target-mips: add CMGCRBase register 



Physical base address for the memory-mapped Coherency Manager Global
Configuration Register space.
The MIPS default location for the GCR_BASE address is 0x1FBF_8.
This register only exists if Config3 CMGCR is set to one.

Signed-off-by: default avatarYongbok Kim <yongbok.kim@imgtec.com>
[leon.alrae@imgtec.com: move CMGCR enabling to a separate patch]
Signed-off-by: default avatarLeon Alrae <leon.alrae@imgtec.com>
parent 8e7e8a5b

target-mips/cpu.h

+2 −1
Original line number Diff line number Diff line
@@ -395,6 +395,7 @@ struct CPUMIPSState { 
    target_ulong CP0_EPC;

    int32_t CP0_PRid;

    int32_t CP0_EBase;

    target_ulong CP0_CMGCRBase;

    int32_t CP0_Config0;

#define CP0C0_M    31

#define CP0C0_K23  28
@@ -437,7 +438,7 @@ struct CPUMIPSState { 
    int32_t CP0_Config3;

#define CP0C3_M    31

#define CP0C3_BPG  30

#define CP0C3_CMCGR 29

#define CP0C3_CMGCR 29

#define CP0C3_MSAP  28

#define CP0C3_BP 27

#define CP0C3_BI 26

target-mips/translate.c

+18 −0
Original line number Diff line number Diff line
@@ -1432,6 +1432,7 @@ typedef struct DisasContext { 
    int CP0_LLAddr_shift;

    bool ps;

    bool vp;

    bool cmgcr;

} DisasContext;









enum {








@@ -5298,6 +5299,13 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)







            gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_EBase));









            rn = "EBase";









            break;









        case 3:









            check_insn(ctx, ISA_MIPS32R2);









            CP0_CHECK(ctx->cmgcr);









            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));









            tcg_gen_ext32s_tl(arg, arg);









            rn = "CMGCRBase";









            break;









        default:









            goto cp0_unimplemented;









       }








@@ -6572,6 +6580,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)







            gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_EBase));









            rn = "EBase";









            break;









        case 3:









            check_insn(ctx, ISA_MIPS32R2);









            CP0_CHECK(ctx->cmgcr);









            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));









            rn = "CMGCRBase";









            break;









        default:









            goto cp0_unimplemented;









        }








@@ -19663,6 +19677,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)







    ctx.PAMask = env->PAMask;









    ctx.mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1;









    ctx.CP0_LLAddr_shift = env->CP0_LLAddr_shift;









    ctx.cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1;









    /* Restore delay slot state from the tb context.  */









    ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */









    ctx.ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;








@@ -20062,6 +20077,9 @@ void cpu_state_reset(CPUMIPSState *env)







    } else {









        env->CP0_EBase |= 0x80000000;









    }









    if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {









        env->CP0_CMGCRBase = 0x1fbf8000 >> 4;









    }









    env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);









    /* vectored interrupts not implemented, timer on int 7,









       no performance counters. */