Commit a805ca54 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into staging 



qemu-sparc update

# gpg: Signature made Wed 21 Jan 2015 16:56:31 GMT using RSA key ID AE0F321F
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>"

* remotes/mcayland/tags/qemu-sparc-signed:
  disas/sparc: Remove unused data sparc_opcode_archs[]
  target-sparc: Mark gen_load_trap_state_at_tl() as !CONFIG_USER_ONLY
  target-sparc: is_translating_asi() is TARGET_SPARC64 only
  target-sparc: address_mask(), asi_address_mask() are TARGET_SPARC64 only
  target-sparc: Remove unused gen_op_subi_cc and gen_op_addi_cc

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 699eae17 7230818a

disas/sparc.c

+0 −32
Original line number Diff line number Diff line
@@ -80,19 +80,6 @@ typedef struct sparc_opcode_arch 
  short supported;

} sparc_opcode_arch;



static const struct sparc_opcode_arch sparc_opcode_archs[];



/* Return the bitmask of supported architectures for ARCH.  */

#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)



/* Non-zero if ARCH1 conflicts with ARCH2.

   IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa.  */

#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \

 (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \

   != SPARC_OPCODE_SUPPORTED (ARCH1)) \

  && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \

     != SPARC_OPCODE_SUPPORTED (ARCH2)))



/* Structure of an opcode table entry.  */



typedef struct sparc_opcode
@@ -301,25 +288,6 @@ static const char *sparc_decode_sparclet_cpreg (int); 
   otherwise.  */

#define v9notv9a        (MASK_V9)



/* Table of opcode architectures.

   The order is defined in opcode/sparc.h.  */



static const struct sparc_opcode_arch sparc_opcode_archs[] =

{

  { "v6", MASK_V6 },

  { "v7", MASK_V6 | MASK_V7 },

  { "v8", MASK_V6 | MASK_V7 | MASK_V8 },

  { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },

  { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },

  /* ??? Don't some v8 privileged insns conflict with v9?  */

  { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },

  /* v9 with ultrasparc additions */

  { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },

  /* v9 with cheetah additions */

  { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },

  { NULL, 0 }

};



/* Branch condition field.  */

#define COND(x)         (((x) & 0xf) << 25)

target-sparc/ldst_helper.c

+5 −5
Original line number Diff line number Diff line
@@ -250,6 +250,7 @@ static void replace_tlb_1bit_lru(SparcTLBEntry *tlb, 


#endif



#if defined(TARGET_SPARC64) || defined(CONFIG_USER_ONLY)

static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr)

{

#ifdef TARGET_SPARC64
@@ -259,12 +260,14 @@ static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr) 
#endif

    return addr;

}

#endif



#ifdef TARGET_SPARC64

/* returns true if access using this ASI is to have address translated by MMU

   otherwise access is to raw physical address */

/* TODO: check sparc32 bits */

static inline int is_translating_asi(int asi)

{

#ifdef TARGET_SPARC64

    /* Ultrasparc IIi translating asi

       - note this list is defined by cpu implementation

    */
@@ -281,10 +284,6 @@ static inline int is_translating_asi(int asi) 
    default:

        return 0;

    }

#else

    /* TODO: check sparc32 bits */

    return 0;

#endif

}



static inline target_ulong asi_address_mask(CPUSPARCState *env,
@@ -296,6 +295,7 @@ static inline target_ulong asi_address_mask(CPUSPARCState *env, 
        return addr;

    }

}

#endif



void helper_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align)

{

target-sparc/translate.c

+2 −24
Original line number Diff line number Diff line
@@ -363,14 +363,6 @@ static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src) 
    tcg_gen_andi_tl(reg, reg, 0x1);

}



static inline void gen_op_addi_cc(TCGv dst, TCGv src1, target_long src2)

{

    tcg_gen_mov_tl(cpu_cc_src, src1);

    tcg_gen_movi_tl(cpu_cc_src2, src2);

    tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_src, src2);

    tcg_gen_mov_tl(dst, cpu_cc_dst);

}



static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)

{

    tcg_gen_mov_tl(cpu_cc_src, src1);
@@ -502,22 +494,6 @@ static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1, 
    }

}



static inline void gen_op_subi_cc(TCGv dst, TCGv src1, target_long src2, DisasContext *dc)

{

    tcg_gen_mov_tl(cpu_cc_src, src1);

    tcg_gen_movi_tl(cpu_cc_src2, src2);

    if (src2 == 0) {

        tcg_gen_mov_tl(cpu_cc_dst, src1);

        tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);

        dc->cc_op = CC_OP_LOGIC;

    } else {

        tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_src, src2);

        tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);

        dc->cc_op = CC_OP_SUB;

    }

    tcg_gen_mov_tl(dst, cpu_cc_dst);

}



static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)

{

    tcg_gen_mov_tl(cpu_cc_src, src1);
@@ -2324,6 +2300,7 @@ static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs) 
    gen_update_fprs_dirty(qd);

}



#ifndef CONFIG_USER_ONLY

static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_ptr cpu_env)

{

    TCGv_i32 r_tl = tcg_temp_new_i32();
@@ -2348,6 +2325,7 @@ static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_ptr cpu_env) 


    tcg_temp_free_i32(r_tl);

}

#endif



static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,

                     int width, bool cc, bool left)