Commit a7b4569a authored by Joel Stanley's avatar Joel Stanley Committed by Peter Maydell
Browse files

aspeed_sdmc: Handle ECC training 



This is required to ensure u-boot SDRAM training completes.

Signed-off-by: default avatarJoel Stanley <joel@jms.id.au>
Reviewed-by: default avatarCédric Le Goater <clg@kaod.org>
Tested-by: default avatarCédric Le Goater <clg@kaod.org>
Message-id: 20180807075757.7242-6-joel@jms.id.au
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 33883ce8

hw/misc/aspeed_sdmc.c

+9 −0
Original line number Diff line number Diff line
@@ -27,6 +27,10 @@ 
#define R_STATUS1         (0x60 / 4)

#define   PHY_BUSY_STATE      BIT(0)



#define R_ECC_TEST_CTRL   (0x70 / 4)

#define   ECC_TEST_FINISHED   BIT(12)

#define   ECC_TEST_FAIL       BIT(13)



/*

 * Configuration register Ox4 (for Aspeed AST2400 SOC)

 *
@@ -148,6 +152,11 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data, 
            /* Will never return 'busy' */

            data &= ~PHY_BUSY_STATE;

            break;

        case R_ECC_TEST_CTRL:

            /* Always done, always happy */

            data |= ECC_TEST_FINISHED;

            data &= ~ECC_TEST_FAIL;

            break;

        default:

            break;

        }