Commit 33883ce8 authored by Joel Stanley's avatar Joel Stanley Committed by Peter Maydell
Browse files

aspeed_sdmc: Init status always idle 



The ast2500 SDRAM training routine busy waits on the 'init cycle busy
state' bit in DDR PHY Control/Status register #1 (MCR60).

This ensures the bit always reads zero, and allows training to
complete with upstream u-boot on the ast2500-evb.

Signed-off-by: default avatarJoel Stanley <joel@jms.id.au>
Reviewed-by: default avatarCédric Le Goater <clg@kaod.org>
Tested-by: default avatarCédric Le Goater <clg@kaod.org>
Message-id: 20180807075757.7242-5-joel@jms.id.au
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent b33f1e0b

hw/misc/aspeed_sdmc.c

+15 −0
Original line number Diff line number Diff line
@@ -23,6 +23,10 @@ 
/* Configuration Register */

#define R_CONF            (0x04 / 4)



/* Control/Status Register #1 (ast2500) */

#define R_STATUS1         (0x60 / 4)

#define   PHY_BUSY_STATE      BIT(0)



/*

 * Configuration register Ox4 (for Aspeed AST2400 SOC)

 *
@@ -137,6 +141,17 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data, 
            g_assert_not_reached();

        }

    }

    if (s->silicon_rev == AST2500_A0_SILICON_REV ||

            s->silicon_rev == AST2500_A1_SILICON_REV) {

        switch (addr) {

        case R_STATUS1:

            /* Will never return 'busy' */

            data &= ~PHY_BUSY_STATE;

            break;

        default:

            break;

        }

    }



    s->regs[addr] = data;

}