Commit b33f1e0b authored by Joel Stanley's avatar Joel Stanley Committed by Peter Maydell
Browse files

aspeed_sdmc: Set 'cache initial sequence' always true 



The SDRAM training routine sets the 'Enable cache initial' bit, and then
waits for the 'cache initial sequence' to be done.

Have it always return done, as there is no other side effects that the
model needs to implement. This allows the upstream u-boot training to
proceed on the ast2500-evb board.

Signed-off-by: default avatarJoel Stanley <joel@jms.id.au>
Reviewed-by: default avatarCédric Le Goater <clg@kaod.org>
Tested-by: default avatarCédric Le Goater <clg@kaod.org>
Message-id: 20180807075757.7242-4-joel@jms.id.au
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent d131bc28

hw/misc/aspeed_sdmc.c

+1 −0
Original line number Diff line number Diff line
@@ -226,6 +226,7 @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp) 
        s->ram_bits = ast2500_rambits(s);

        s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) |

            ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |

            ASPEED_SDMC_CACHE_INITIAL_DONE |

            ASPEED_SDMC_DRAM_SIZE(s->ram_bits);

        break;

    default: