Commit 9ec34ecc authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.1-20190426' into staging 



ppc patch queue 2019-04-26

Here's the first ppc target pull request for qemu-4.1.  This has a
number of things that have accumulated while qemu-4.0 was frozen.

 * A number of emulated MMU improvements from Ben Herrenschmidt

 * Assorted cleanups fro Greg Kurz

 * A large set of mostly mechanical cleanups from me to make target/ppc
   much closer to compliant with the modern coding style

 * Support for passthrough of NVIDIA GPUs using NVLink2

As well as some other assorted fixes.

# gpg: Signature made Fri 26 Apr 2019 07:02:19 BST
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full]
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-4.1-20190426: (36 commits)
  target/ppc: improve performance of large BAT invalidations
  ppc/hash32: Rework R and C bit updates
  ppc/hash64: Rework R and C bit updates
  ppc/spapr: Use proper HPTE accessors for H_READ
  target/ppc: Don't check UPRT in radix mode when in HV real mode
  target/ppc/kvm: Convert DPRINTF to traces
  target/ppc/trace-events: Fix trivial typo
  spapr: Drop duplicate PCI swizzle code
  spapr_pci: Get rid of duplicate code for node name creation
  target/ppc: Style fixes for translate/spe-impl.inc.c
  target/ppc: Style fixes for translate/vmx-impl.inc.c
  target/ppc: Style fixes for translate/vsx-impl.inc.c
  target/ppc: Style fixes for translate/fp-impl.inc.c
  target/ppc: Style fixes for translate.c
  target/ppc: Style fixes for translate_init.inc.c
  target/ppc: Style fixes for monitor.c
  target/ppc: Style fixes for mmu_helper.c
  target/ppc: Style fixes for mmu-hash64.[ch]
  target/ppc: Style fixes for mmu-hash32.[ch]
  target/ppc: Style fixes for misc_helper.c
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents db7f1c3f aaef873b

hw/pci/pci.c

+1 −1
Original line number Diff line number Diff line
@@ -1556,7 +1556,7 @@ void pci_device_set_intx_routing_notifier(PCIDevice *dev, 
 */

int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)

{

    return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;

    return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin);

}



/***********************************************************/

hw/ppc/Makefile.objs

+1 −1
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ obj-$(CONFIG_SPAPR_RNG) += spapr_rng.o 
# IBM PowerNV

obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o pnv_occ.o pnv_bmc.o

ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy)

obj-y += spapr_pci_vfio.o

obj-y += spapr_pci_vfio.o spapr_pci_nvlink2.o

endif

obj-$(CONFIG_PSERIES) += spapr_rtas_ddw.o

# PowerPC 4xx boards

hw/ppc/prep.c

+0 −1
Original line number Diff line number Diff line
@@ -40,7 +40,6 @@ 
#include "hw/ide.h"

#include "hw/loader.h"

#include "hw/timer/mc146818rtc.h"

#include "hw/input/i8042.h"

#include "hw/isa/pc87312.h"

#include "hw/net/ne2000-isa.h"

#include "sysemu/arch_init.h"

hw/ppc/spapr.c

+78 −11
Original line number Diff line number Diff line
@@ -1034,12 +1034,13 @@ static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 
        0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),

        cpu_to_be32(max_cpus / smp_threads),

    };

    uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0);

    uint32_t maxdomains[] = {

        cpu_to_be32(4),

        cpu_to_be32(0),

        cpu_to_be32(0),

        cpu_to_be32(0),

        cpu_to_be32(nb_numa_nodes ? nb_numa_nodes : 1),

        maxdomain,

        maxdomain,

        maxdomain,

        cpu_to_be32(spapr->gpu_numa_id),

    };



    _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
@@ -1519,10 +1520,10 @@ static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 
    /* Nothing to do for qemu managed HPT */

}



static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex,

void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,

                      uint64_t pte0, uint64_t pte1)

{

    SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);

    SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp);

    hwaddr offset = ptex * HASH_PTE_SIZE_64;



    if (!spapr->htab) {
@@ -1550,6 +1551,38 @@ static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 
    }

}



static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex,

                             uint64_t pte1)

{

    hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15;

    SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);



    if (!spapr->htab) {

        /* There should always be a hash table when this is called */

        error_report("spapr_hpte_set_c called with no hash table !");

        return;

    }



    /* The HW performs a non-atomic byte update */

    stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80);

}



static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex,

                             uint64_t pte1)

{

    hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14;

    SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);



    if (!spapr->htab) {

        /* There should always be a hash table when this is called */

        error_report("spapr_hpte_set_r called with no hash table !");

        return;

    }



    /* The HW performs a non-atomic byte update */

    stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01);

}



int spapr_hpt_shift_for_ramsize(uint64_t ramsize)

{

    int shift;
@@ -1698,6 +1731,16 @@ static void spapr_machine_reset(void) 
        spapr_irq_msi_reset(spapr);

    }



    /*

     * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.

     * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is

     * called from vPHB reset handler so we initialize the counter here.

     * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM

     * must be equally distant from any other node.

     * The final value of spapr->gpu_numa_id is going to be written to

     * max-associativity-domains in spapr_build_fdt().

     */

    spapr->gpu_numa_id = MAX(1, nb_numa_nodes);

    qemu_devices_reset();



    /*
@@ -3907,7 +3950,9 @@ static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 
    smc->phb_placement(spapr, sphb->index,

                       &sphb->buid, &sphb->io_win_addr,

                       &sphb->mem_win_addr, &sphb->mem64_win_addr,

                       windows_supported, sphb->dma_liobn, errp);

                       windows_supported, sphb->dma_liobn,

                       &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr,

                       errp);

}



static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
@@ -4108,7 +4153,8 @@ static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 
static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index,

                                uint64_t *buid, hwaddr *pio,

                                hwaddr *mmio32, hwaddr *mmio64,

                                unsigned n_dma, uint32_t *liobns, Error **errp)

                                unsigned n_dma, uint32_t *liobns,

                                hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp)

{

    /*

     * New-style PHB window placement.
@@ -4153,6 +4199,9 @@ static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 
    *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;

    *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;

    *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;



    *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE;

    *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE;

}



static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
@@ -4274,7 +4323,8 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) 
    vhc->hpt_mask = spapr_hpt_mask;

    vhc->map_hptes = spapr_map_hptes;

    vhc->unmap_hptes = spapr_unmap_hptes;

    vhc->store_hpte = spapr_store_hpte;

    vhc->hpte_set_c = spapr_hpte_set_c;

    vhc->hpte_set_r = spapr_hpte_set_r;

    vhc->get_pate = spapr_get_pate;

    vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr;

    xic->ics_get = spapr_ics_get;
@@ -4368,6 +4418,18 @@ DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 
/*

 * pseries-3.1

 */

static void phb_placement_3_1(SpaprMachineState *spapr, uint32_t index,

                              uint64_t *buid, hwaddr *pio,

                              hwaddr *mmio32, hwaddr *mmio64,

                              unsigned n_dma, uint32_t *liobns,

                              hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp)

{

    spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns,

                        nv2gpa, nv2atsd, errp);

    *nv2gpa = 0;

    *nv2atsd = 0;

}



static void spapr_machine_3_1_class_options(MachineClass *mc)

{

    SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
@@ -4383,6 +4445,7 @@ static void spapr_machine_3_1_class_options(MachineClass *mc) 
    smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN;

    smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN;

    smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF;

    smc->phb_placement = phb_placement_3_1;

}



DEFINE_SPAPR_MACHINE(3_1, "3.1", false);
@@ -4514,7 +4577,8 @@ DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 
static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index,

                              uint64_t *buid, hwaddr *pio,

                              hwaddr *mmio32, hwaddr *mmio64,

                              unsigned n_dma, uint32_t *liobns, Error **errp)

                              unsigned n_dma, uint32_t *liobns,

                              hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp)

{

    /* Legacy PHB placement for pseries-2.7 and earlier machine types */

    const uint64_t base_buid = 0x800000020000000ULL;
@@ -4558,6 +4622,9 @@ static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 
     * fallback behaviour of automatically splitting a large "32-bit"

     * window into contiguous 32-bit and 64-bit windows

     */



    *nv2gpa = 0;

    *nv2atsd = 0;

}



static void spapr_machine_2_7_class_options(MachineClass *mc)

hw/ppc/spapr_hcall.c

+12 −12
Original line number Diff line number Diff line
@@ -118,7 +118,7 @@ static target_ulong h_enter(PowerPCCPU *cpu, SpaprMachineState *spapr, 
        ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);

    }



    ppc_hash64_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel);

    spapr_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel);



    args[0] = ptex + slot;

    return H_SUCCESS;
@@ -131,7 +131,8 @@ typedef enum { 
    REMOVE_HW = 3,

} RemoveResult;



static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex,

static RemoveResult remove_hpte(PowerPCCPU *cpu

                                , target_ulong ptex,

                                target_ulong avpn,

                                target_ulong flags,

                                target_ulong *vp, target_ulong *rp)
@@ -155,7 +156,7 @@ static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex, 
    }

    *vp = v;

    *rp = r;

    ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0);

    spapr_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0);

    ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r);

    return REMOVE_SUCCESS;

}
@@ -289,13 +290,13 @@ static target_ulong h_protect(PowerPCCPU *cpu, SpaprMachineState *spapr, 
    r |= (flags << 55) & HPTE64_R_PP0;

    r |= (flags << 48) & HPTE64_R_KEY_HI;

    r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO);

    ppc_hash64_store_hpte(cpu, ptex,

    spapr_store_hpte(cpu, ptex,

                     (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0);

    ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r);

    /* Flush the tlb */

    check_tlb_flush(env, true);

    /* Don't need a memory barrier, due to qemu's global lock */

    ppc_hash64_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r);

    spapr_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r);

    return H_SUCCESS;

}
@@ -304,8 +305,8 @@ static target_ulong h_read(PowerPCCPU *cpu, SpaprMachineState *spapr, 
{

    target_ulong flags = args[0];

    target_ulong ptex = args[1];

    uint8_t *hpte;

    int i, ridx, n_entries = 1;

    const ppc_hash_pte64_t *hptes;



    if (!valid_ptex(cpu, ptex)) {

        return H_PARAMETER;
@@ -317,13 +318,12 @@ static target_ulong h_read(PowerPCCPU *cpu, SpaprMachineState *spapr, 
        n_entries = 4;

    }



    hpte = spapr->htab + (ptex * HASH_PTE_SIZE_64);



    hptes = ppc_hash64_map_hptes(cpu, ptex, n_entries);

    for (i = 0, ridx = 0; i < n_entries; i++) {

        args[ridx++] = ldq_p(hpte);

        args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2));

        hpte += HASH_PTE_SIZE_64;

        args[ridx++] = ppc_hash64_hpte0(cpu, hptes, i);

        args[ridx++] = ppc_hash64_hpte1(cpu, hptes, i);

    }

    ppc_hash64_unmap_hptes(cpu, hptes, ptex, n_entries);



    return H_SUCCESS;

}