Commit db7f1c3f authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' into staging 



x86 queue, 2019-04-25

* Hygon Dhyana CPU model (Pu Wen)
* Categorize a few devices in hw/i386 (Ernest Esene)
* Support host-cache-info on TOPOEXT CPUID leaf (Stanislav Lanci)

# gpg: Signature made Thu 25 Apr 2019 19:12:25 BST
# gpg:                using RSA key 2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-next-pull-request:
  Pass through cache information for TOPOEXT CPUs
  Categorize devices: iommu
  Categorize devices: IGD passthrough ISA bridge
  i386: Add new Hygon 'Dhyana' CPU model

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 06e64339 a4e0b436

hw/i386/amd_iommu.c

+2 −0
Original line number Diff line number Diff line
@@ -1601,6 +1601,8 @@ static void amdvi_class_init(ObjectClass *klass, void* data) 
    dc_class->int_remap = amdvi_int_remap;

    /* Supported by the pc-q35-* machine types */

    dc->user_creatable = true;

    set_bit(DEVICE_CATEGORY_MISC, dc->categories);

    dc->desc = "AMD IOMMU (AMD-Vi) DMA Remapping device";

}



static const TypeInfo amdvi = {

hw/i386/intel_iommu.c

+2 −0
Original line number Diff line number Diff line
@@ -3741,6 +3741,8 @@ static void vtd_class_init(ObjectClass *klass, void *data) 
    x86_class->int_remap = vtd_int_remap;

    /* Supported by the pc-q35-* machine types */

    dc->user_creatable = true;

    set_bit(DEVICE_CATEGORY_MISC, dc->categories);

    dc->desc = "Intel IOMMU (VT-d) DMA Remapping device";

}



static const TypeInfo vtd_info = {

hw/i386/pc_piix.c

+1 −0
Original line number Diff line number Diff line
@@ -923,6 +923,7 @@ static void isa_bridge_class_init(ObjectClass *klass, void *data) 
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);



    dc->desc        = "ISA bridge faked to support IGD PT";

    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);

    k->vendor_id    = PCI_VENDOR_ID_INTEL;

    k->class_id     = PCI_CLASS_BRIDGE_ISA;

};

target/i386/cpu.c

+54 −0
Original line number Diff line number Diff line
@@ -2935,6 +2935,56 @@ static X86CPUDefinition builtin_x86_defs[] = { 
        .model_id = "AMD EPYC Processor (with IBPB)",

        .cache_info = &epyc_cache_info,

    },

    {

        .name = "Dhyana",

        .level = 0xd,

        .vendor = CPUID_VENDOR_HYGON,

        .family = 24,

        .model = 0,

        .stepping = 1,

        .features[FEAT_1_EDX] =

            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |

            CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |

            CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |

            CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |

            CPUID_VME | CPUID_FP87,

        .features[FEAT_1_ECX] =

            CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |

            CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |

            CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |

            CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |

            CPUID_EXT_MONITOR | CPUID_EXT_SSE3,

        .features[FEAT_8000_0001_EDX] =

            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |

            CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |

            CPUID_EXT2_SYSCALL,

        .features[FEAT_8000_0001_ECX] =

            CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |

            CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |

            CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |

            CPUID_EXT3_TOPOEXT,

        .features[FEAT_8000_0008_EBX] =

            CPUID_8000_0008_EBX_IBPB,

        .features[FEAT_7_0_EBX] =

            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |

            CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |

            CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,

        /*

         * Missing: XSAVES (not supported by some Linux versions,

         * including v4.1 to v4.12).

         * KVM doesn't yet expose any XSAVES state save component.

         */

        .features[FEAT_XSAVE] =

            CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |

            CPUID_XSAVE_XGETBV1,

        .features[FEAT_6_EAX] =

            CPUID_6_EAX_ARAT,

        .features[FEAT_SVM] =

            CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,

        .xlevel = 0x8000001E,

        .model_id = "Hygon Dhyana Processor",

        .cache_info = &epyc_cache_info,

    },

};



typedef struct PropValue {
@@ -4541,6 +4591,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 
        break;

    case 0x8000001D:

        *eax = 0;

        if (cpu->cache_info_passthrough) {

            host_cpuid(index, count, eax, ebx, ecx, edx);

            break;

        }

        switch (count) {

        case 0: /* L1 dcache info */

            encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,

target/i386/cpu.h

+2 −0
Original line number Diff line number Diff line
@@ -726,6 +726,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 


#define CPUID_VENDOR_VIA   "CentaurHauls"



#define CPUID_VENDOR_HYGON    "HygonGenuine"



#define CPUID_MWAIT_IBE     (1U << 1) /* Interrupts can exit capability */

#define CPUID_MWAIT_EMX     (1U << 0) /* enumeration supported */