Commit 9bed46e6 authored by Tony Nguyen's avatar Tony Nguyen Committed by Richard Henderson
Browse files

target/sparc: Add TLB entry with attributes 



Append MemTxAttrs to interfaces so we can pass along up coming Invert
Endian TTE bit on SPARC64.

Signed-off-by: default avatarTony Nguyen <tony.nguyen@bt.com>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-Id: <f8fcc3138570c460ef289a6b34ba7715ba36f99e.1566466906.git.tony.nguyen@bt.com>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent a26fc6f5

target/sparc/mmu_helper.c

+18 −14
Original line number Diff line number Diff line
@@ -88,7 +88,7 @@ static const int perm_table[2][8] = { 
};



static int get_physical_address(CPUSPARCState *env, hwaddr *physical,

                                int *prot, int *access_index,

                                int *prot, int *access_index, MemTxAttrs *attrs,

                                target_ulong address, int rw, int mmu_idx,

                                target_ulong *page_size)

{
@@ -219,6 +219,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 
    target_ulong vaddr;

    target_ulong page_size;

    int error_code = 0, prot, access_index;

    MemTxAttrs attrs = {};



    /*

     * TODO: If we ever need tlb_vaddr_to_host for this target,
@@ -229,7 +230,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 
    assert(!probe);



    address &= TARGET_PAGE_MASK;

    error_code = get_physical_address(env, &paddr, &prot, &access_index,

    error_code = get_physical_address(env, &paddr, &prot, &access_index, &attrs,

                                      address, access_type,

                                      mmu_idx, &page_size);

    vaddr = address;
@@ -490,8 +491,8 @@ static inline int ultrasparc_tag_match(SparcTLBEntry *tlb, 
    return 0;

}



static int get_physical_address_data(CPUSPARCState *env,

                                     hwaddr *physical, int *prot,

static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical,

                                     int *prot, MemTxAttrs *attrs,

                                     target_ulong address, int rw, int mmu_idx)

{

    CPUState *cs = env_cpu(env);
@@ -608,8 +609,8 @@ static int get_physical_address_data(CPUSPARCState *env, 
    return 1;

}



static int get_physical_address_code(CPUSPARCState *env,

                                     hwaddr *physical, int *prot,

static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical,

                                     int *prot, MemTxAttrs *attrs,

                                     target_ulong address, int mmu_idx)

{

    CPUState *cs = env_cpu(env);
@@ -686,7 +687,7 @@ static int get_physical_address_code(CPUSPARCState *env, 
}



static int get_physical_address(CPUSPARCState *env, hwaddr *physical,

                                int *prot, int *access_index,

                                int *prot, int *access_index, MemTxAttrs *attrs,

                                target_ulong address, int rw, int mmu_idx,

                                target_ulong *page_size)

{
@@ -716,11 +717,11 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, 
    }



    if (rw == 2) {

        return get_physical_address_code(env, physical, prot, address,

        return get_physical_address_code(env, physical, prot, attrs, address,

                                         mmu_idx);

    } else {

        return get_physical_address_data(env, physical, prot, address, rw,

                                         mmu_idx);

        return get_physical_address_data(env, physical, prot, attrs, address,

                                         rw, mmu_idx);

    }

}
@@ -734,10 +735,11 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 
    target_ulong vaddr;

    hwaddr paddr;

    target_ulong page_size;

    MemTxAttrs attrs = {};

    int error_code = 0, prot, access_index;



    address &= TARGET_PAGE_MASK;

    error_code = get_physical_address(env, &paddr, &prot, &access_index,

    error_code = get_physical_address(env, &paddr, &prot, &access_index, &attrs,

                                      address, access_type,

                                      mmu_idx, &page_size);

    if (likely(error_code == 0)) {
@@ -747,7 +749,8 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 
                                   env->dmmu.mmu_primary_context,

                                   env->dmmu.mmu_secondary_context);



        tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);

        tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, prot, mmu_idx,

                                page_size);

        return true;

    }

    if (probe) {
@@ -849,9 +852,10 @@ static int cpu_sparc_get_phys_page(CPUSPARCState *env, hwaddr *phys, 
{

    target_ulong page_size;

    int prot, access_index;

    MemTxAttrs attrs = {};



    return get_physical_address(env, phys, &prot, &access_index, addr, rw,

                                mmu_idx, &page_size);

    return get_physical_address(env, phys, &prot, &access_index, &attrs, addr,

                                rw, mmu_idx, &page_size);

}



#if defined(TARGET_SPARC64)