Commit 93193190 authored by Alex Bennée's avatar Alex Bennée Committed by Peter Maydell
Browse files

arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16 



I've re-factored the handle_simd_intfp_conv helper to properly handle
half-precision as well as call plain conversion helpers when we are
not doing fixed point conversion.

Signed-off-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-21-alex.bennee@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 7d4dd1a7

target/arm/helper.c

+4 −0
Original line number Diff line number Diff line
@@ -11302,8 +11302,10 @@ CONV_ITOF(vfp_##name##to##p, fsz, sign) \ 
CONV_FTOI(vfp_to##name##p, fsz, sign, ) \

CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)



FLOAT_CONVS(si, h, 16, )

FLOAT_CONVS(si, s, 32, )

FLOAT_CONVS(si, d, 64, )

FLOAT_CONVS(ui, h, 16, u)

FLOAT_CONVS(ui, s, 32, u)

FLOAT_CONVS(ui, d, 64, u)
@@ -11386,6 +11388,8 @@ VFP_CONV_FIX_A64(sq, s, 32, 64, int64) 
VFP_CONV_FIX(uh, s, 32, 32, uint16)

VFP_CONV_FIX(ul, s, 32, 32, uint32)

VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)

VFP_CONV_FIX_A64(sl, h, 16, 32, int32)

VFP_CONV_FIX_A64(ul, h, 16, 32, uint32)

#undef VFP_CONV_FIX

#undef VFP_CONV_FIX_FLOAT

#undef VFP_CONV_FLOAT_FIX_ROUND

target/arm/helper.h

+10 −0
Original line number Diff line number Diff line
@@ -120,17 +120,23 @@ DEF_HELPER_3(vfp_cmped, void, f64, f64, env) 
DEF_HELPER_2(vfp_fcvtds, f64, f32, env)

DEF_HELPER_2(vfp_fcvtsd, f32, f64, env)



DEF_HELPER_2(vfp_uitoh, f16, i32, ptr)

DEF_HELPER_2(vfp_uitos, f32, i32, ptr)

DEF_HELPER_2(vfp_uitod, f64, i32, ptr)

DEF_HELPER_2(vfp_sitoh, f16, i32, ptr)

DEF_HELPER_2(vfp_sitos, f32, i32, ptr)

DEF_HELPER_2(vfp_sitod, f64, i32, ptr)



DEF_HELPER_2(vfp_touih, i32, f16, ptr)

DEF_HELPER_2(vfp_touis, i32, f32, ptr)

DEF_HELPER_2(vfp_touid, i32, f64, ptr)

DEF_HELPER_2(vfp_touizh, i32, f16, ptr)

DEF_HELPER_2(vfp_touizs, i32, f32, ptr)

DEF_HELPER_2(vfp_touizd, i32, f64, ptr)

DEF_HELPER_2(vfp_tosih, i32, f16, ptr)

DEF_HELPER_2(vfp_tosis, i32, f32, ptr)

DEF_HELPER_2(vfp_tosid, i32, f64, ptr)

DEF_HELPER_2(vfp_tosizh, i32, f16, ptr)

DEF_HELPER_2(vfp_tosizs, i32, f32, ptr)

DEF_HELPER_2(vfp_tosizd, i32, f64, ptr)
@@ -142,6 +148,8 @@ DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, ptr) 
DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr)

DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)

DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)

DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)

DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)

DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)

DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)

DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
@@ -166,6 +174,8 @@ DEF_HELPER_3(vfp_sqtod, f64, i64, i32, ptr) 
DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr)

DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)

DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)

DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)

DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)



DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)

DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)

target/arm/translate-a64.c

+90 −24
Original line number Diff line number Diff line
@@ -6902,23 +6902,28 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, 
                                   int elements, int is_signed,

                                   int fracbits, int size)

{

    bool is_double = size == 3 ? true : false;

    TCGv_ptr tcg_fpst = get_fpstatus_ptr(false);

    TCGv_i32 tcg_shift = tcg_const_i32(fracbits);

    TCGv_i64 tcg_int = tcg_temp_new_i64();

    TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_16);

    TCGv_i32 tcg_shift = NULL;



    TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);

    int pass;



    for (pass = 0; pass < elements; pass++) {

        read_vec_element(s, tcg_int, rn, pass, mop);

    if (fracbits || size == MO_64) {

        tcg_shift = tcg_const_i32(fracbits);

    }



        if (is_double) {

    if (size == MO_64) {

        TCGv_i64 tcg_int64 = tcg_temp_new_i64();

        TCGv_i64 tcg_double = tcg_temp_new_i64();



        for (pass = 0; pass < elements; pass++) {

            read_vec_element(s, tcg_int64, rn, pass, mop);



            if (is_signed) {

                gen_helper_vfp_sqtod(tcg_double, tcg_int,

                gen_helper_vfp_sqtod(tcg_double, tcg_int64,

                                     tcg_shift, tcg_fpst);

            } else {

                gen_helper_vfp_uqtod(tcg_double, tcg_int,

                gen_helper_vfp_uqtod(tcg_double, tcg_int64,

                                     tcg_shift, tcg_fpst);

            }

            if (elements == 1) {
@@ -6926,28 +6931,72 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, 
            } else {

                write_vec_element(s, tcg_double, rd, pass, MO_64);

            }

        }



        tcg_temp_free_i64(tcg_int64);

        tcg_temp_free_i64(tcg_double);



    } else {

            TCGv_i32 tcg_single = tcg_temp_new_i32();

        TCGv_i32 tcg_int32 = tcg_temp_new_i32();

        TCGv_i32 tcg_float = tcg_temp_new_i32();



        for (pass = 0; pass < elements; pass++) {

            read_vec_element_i32(s, tcg_int32, rn, pass, mop);



            switch (size) {

            case MO_32:

                if (fracbits) {

                    if (is_signed) {

                gen_helper_vfp_sqtos(tcg_single, tcg_int,

                        gen_helper_vfp_sltos(tcg_float, tcg_int32,

                                             tcg_shift, tcg_fpst);

                    } else {

                gen_helper_vfp_uqtos(tcg_single, tcg_int,

                        gen_helper_vfp_ultos(tcg_float, tcg_int32,

                                             tcg_shift, tcg_fpst);

                    }

                } else {

                    if (is_signed) {

                        gen_helper_vfp_sitos(tcg_float, tcg_int32, tcg_fpst);

                    } else {

                        gen_helper_vfp_uitos(tcg_float, tcg_int32, tcg_fpst);

                    }

                }

                break;

            case MO_16:

                if (fracbits) {

                    if (is_signed) {

                        gen_helper_vfp_sltoh(tcg_float, tcg_int32,

                                             tcg_shift, tcg_fpst);

                    } else {

                        gen_helper_vfp_ultoh(tcg_float, tcg_int32,

                                             tcg_shift, tcg_fpst);

                    }

                } else {

                    if (is_signed) {

                        gen_helper_vfp_sitoh(tcg_float, tcg_int32, tcg_fpst);

                    } else {

                        gen_helper_vfp_uitoh(tcg_float, tcg_int32, tcg_fpst);

                    }

                }

                break;

            default:

                g_assert_not_reached();

            }



            if (elements == 1) {

                write_fp_sreg(s, rd, tcg_single);

                write_fp_sreg(s, rd, tcg_float);

            } else {

                write_vec_element_i32(s, tcg_single, rd, pass, MO_32);

                write_vec_element_i32(s, tcg_float, rd, pass, size);

            }

            tcg_temp_free_i32(tcg_single);

        }



        tcg_temp_free_i32(tcg_int32);

        tcg_temp_free_i32(tcg_float);

    }



    tcg_temp_free_i64(tcg_int);

    tcg_temp_free_ptr(tcg_fpst);

    if (tcg_shift) {

        tcg_temp_free_i32(tcg_shift);

    }



    clear_vec_high(s, elements << size == 16, rd);

}
@@ -11236,6 +11285,23 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) 
    rn = extract32(insn, 5, 5);



    switch (fpop) {

    case 0x1d: /* SCVTF */

    case 0x5d: /* UCVTF */

    {

        int elements;



        if (is_scalar) {

            elements = 1;

        } else {

            elements = (is_q ? 8 : 4);

        }



        if (!fp_access_check(s)) {

            return;

        }

        handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16);

        return;

    }

    break;

    case 0x2c: /* FCMGT (zero) */

    case 0x2d: /* FCMEQ (zero) */