Commit 7d4dd1a7 authored by Alex Bennée's avatar Alex Bennée Committed by Peter Maydell
Browse files

arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16 



I re-use the existing handle_2misc_fcmp_zero handler and tweak it
slightly to deal with the half-precision case.

Signed-off-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-20-alex.bennee@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 2df58130

target/arm/translate-a64.c

+57 −23
Original line number Diff line number Diff line
@@ -7821,14 +7821,14 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, 
                                   bool is_scalar, bool is_u, bool is_q,

                                   int size, int rn, int rd)

{

    bool is_double = (size == 3);

    bool is_double = (size == MO_64);

    TCGv_ptr fpst;



    if (!fp_access_check(s)) {

        return;

    }



    fpst = get_fpstatus_ptr(false);

    fpst = get_fpstatus_ptr(size == MO_16);



    if (is_double) {

        TCGv_i64 tcg_op = tcg_temp_new_i64();
@@ -7880,6 +7880,27 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, 
        bool swap = false;

        int pass, maxpasses;



        if (size == MO_16) {

            switch (opcode) {

            case 0x2e: /* FCMLT (zero) */

                swap = true;

                /* fall through */

            case 0x2c: /* FCMGT (zero) */

                genfn = gen_helper_advsimd_cgt_f16;

                break;

            case 0x2d: /* FCMEQ (zero) */

                genfn = gen_helper_advsimd_ceq_f16;

                break;

            case 0x6d: /* FCMLE (zero) */

                swap = true;

                /* fall through */

            case 0x6c: /* FCMGE (zero) */

                genfn = gen_helper_advsimd_cge_f16;

                break;

            default:

                g_assert_not_reached();

            }

        } else {

            switch (opcode) {

            case 0x2e: /* FCMLT (zero) */

                swap = true;
@@ -7899,15 +7920,17 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, 
            default:

                g_assert_not_reached();

            }

        }



        if (is_scalar) {

            maxpasses = 1;

        } else {

            maxpasses = is_q ? 4 : 2;

            int vector_size = 8 << is_q;

            maxpasses = vector_size >> size;

        }



        for (pass = 0; pass < maxpasses; pass++) {

            read_vec_element_i32(s, tcg_op, rn, pass, MO_32);

            read_vec_element_i32(s, tcg_op, rn, pass, size);

            if (swap) {

                genfn(tcg_res, tcg_zero, tcg_op, fpst);

            } else {
@@ -7916,7 +7939,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, 
            if (is_scalar) {

                write_fp_sreg(s, rd, tcg_res);

            } else {

                write_vec_element_i32(s, tcg_res, rd, pass, MO_32);

                write_vec_element_i32(s, tcg_res, rd, pass, size);

            }

        }

        tcg_temp_free_i32(tcg_res);
@@ -11209,7 +11232,18 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) 
    fpop = deposit32(opcode, 5, 1, a);

    fpop = deposit32(fpop, 6, 1, u);



    rd = extract32(insn, 0, 5);

    rn = extract32(insn, 5, 5);



    switch (fpop) {

    break;

    case 0x2c: /* FCMGT (zero) */

    case 0x2d: /* FCMEQ (zero) */

    case 0x2e: /* FCMLT (zero) */

    case 0x6c: /* FCMGE (zero) */

    case 0x6d: /* FCMLE (zero) */

        handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);

        return;

    case 0x18: /* FRINTN */

        need_rmode = true;

        only_in_vector = true;