Commit 2df58130 authored by Alex Bennée's avatar Alex Bennée Committed by Peter Maydell
Browse files

arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16 



This covers all the floating point convert operations.

Signed-off-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-19-alex.bennee@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 6109aea2

target/arm/helper-a64.c

+32 −0
Original line number Diff line number Diff line
@@ -767,3 +767,35 @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status) 


    return ret;

}



/*

 * Half-precision floating point conversion functions

 *

 * There are a multitude of conversion functions with various

 * different rounding modes. This is dealt with by the calling code

 * setting the mode appropriately before calling the helper.

 */



uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)

{

    float_status *fpst = fpstp;



    /* Invalid if we are passed a NaN */

    if (float16_is_any_nan(a)) {

        float_raise(float_flag_invalid, fpst);

        return 0;

    }

    return float16_to_int16(a, fpst);

}



uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)

{

    float_status *fpst = fpstp;



    /* Invalid if we are passed a NaN */

    if (float16_is_any_nan(a)) {

        float_raise(float_flag_invalid, fpst);

        return 0;

    }

    return float16_to_uint16(a, fpst);

}

target/arm/helper-a64.h

+2 −0
Original line number Diff line number Diff line
@@ -77,3 +77,5 @@ DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr) 
DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)

DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)

DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)

DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)

DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)

target/arm/translate-a64.c

+84 −1
Original line number Diff line number Diff line
@@ -11240,6 +11240,46 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) 
        only_in_vector = true;

        /* current rounding mode */

        break;

    case 0x1a: /* FCVTNS */

        need_rmode = true;

        rmode = FPROUNDING_TIEEVEN;

        break;

    case 0x1b: /* FCVTMS */

        need_rmode = true;

        rmode = FPROUNDING_NEGINF;

        break;

    case 0x1c: /* FCVTAS */

        need_rmode = true;

        rmode = FPROUNDING_TIEAWAY;

        break;

    case 0x3a: /* FCVTPS */

        need_rmode = true;

        rmode = FPROUNDING_POSINF;

        break;

    case 0x3b: /* FCVTZS */

        need_rmode = true;

        rmode = FPROUNDING_ZERO;

        break;

    case 0x5a: /* FCVTNU */

        need_rmode = true;

        rmode = FPROUNDING_TIEEVEN;

        break;

    case 0x5b: /* FCVTMU */

        need_rmode = true;

        rmode = FPROUNDING_NEGINF;

        break;

    case 0x5c: /* FCVTAU */

        need_rmode = true;

        rmode = FPROUNDING_TIEAWAY;

        break;

    case 0x7a: /* FCVTPU */

        need_rmode = true;

        rmode = FPROUNDING_POSINF;

        break;

    case 0x7b: /* FCVTZU */

        need_rmode = true;

        rmode = FPROUNDING_ZERO;

        break;

    default:

        fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);

        g_assert_not_reached();
@@ -11273,7 +11313,36 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) 
    }



    if (is_scalar) {

        /* no operations yet */

        TCGv_i32 tcg_op = tcg_temp_new_i32();

        TCGv_i32 tcg_res = tcg_temp_new_i32();



        read_vec_element_i32(s, tcg_op, rn, 0, MO_16);



        switch (fpop) {

        case 0x1a: /* FCVTNS */

        case 0x1b: /* FCVTMS */

        case 0x1c: /* FCVTAS */

        case 0x3a: /* FCVTPS */

        case 0x3b: /* FCVTZS */

            gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);

            break;

        case 0x5a: /* FCVTNU */

        case 0x5b: /* FCVTMU */

        case 0x5c: /* FCVTAU */

        case 0x7a: /* FCVTPU */

        case 0x7b: /* FCVTZU */

            gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);

            break;

        default:

            g_assert_not_reached();

        }



        /* limit any sign extension going on */

        tcg_gen_andi_i32(tcg_res, tcg_res, 0xffff);

        write_fp_sreg(s, rd, tcg_res);



        tcg_temp_free_i32(tcg_res);

        tcg_temp_free_i32(tcg_op);

    } else {

        for (pass = 0; pass < (is_q ? 8 : 4); pass++) {

            TCGv_i32 tcg_op = tcg_temp_new_i32();
@@ -11282,6 +11351,20 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) 
            read_vec_element_i32(s, tcg_op, rn, pass, MO_16);



            switch (fpop) {

            case 0x1a: /* FCVTNS */

            case 0x1b: /* FCVTMS */

            case 0x1c: /* FCVTAS */

            case 0x3a: /* FCVTPS */

            case 0x3b: /* FCVTZS */

                gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);

                break;

            case 0x5a: /* FCVTNU */

            case 0x5b: /* FCVTMU */

            case 0x5c: /* FCVTAU */

            case 0x7a: /* FCVTPU */

            case 0x7b: /* FCVTZU */

                gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);

                break;

            case 0x18: /* FRINTN */

            case 0x19: /* FRINTM */

            case 0x38: /* FRINTP */