Loading target/arm/translate-vfp.inc.c +28 −0 Original line number Diff line number Diff line Loading @@ -2426,3 +2426,31 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a) tcg_temp_free_ptr(fpst); return true; } static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) { TCGv_i32 vd; TCGv_i64 vm; if (!dc_isar_feature(aa32_jscvt, s)) { return false; } /* UNDEF accesses to D16-D31 if they don't exist. */ if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { return false; } if (!vfp_access_check(s)) { return true; } vm = tcg_temp_new_i64(); vd = tcg_temp_new_i32(); neon_load_reg64(vm, a->vm); gen_helper_vjcvt(vd, vm, cpu_env); neon_store_reg32(vd, a->vd); tcg_temp_free_i64(vm); tcg_temp_free_i32(vd); return true; } target/arm/translate.c +1 −11 Original line number Diff line number Diff line Loading @@ -3050,7 +3050,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) return 1; case 15: switch (rn) { case 0 ... 17: case 0 ... 19: /* Already handled by decodetree */ return 1; default: Loading Loading @@ -3085,13 +3085,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) rm_is_dp = false; break; case 0x13: /* vjcvt */ if (!dp || !dc_isar_feature(aa32_jscvt, s)) { return 1; } rd_is_dp = false; break; default: return 1; } Loading Loading @@ -3177,9 +3170,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) switch (op) { case 15: /* extension space */ switch (rn) { case 19: /* vjcvt */ gen_helper_vjcvt(cpu_F0s, cpu_F0d, cpu_env); break; case 20: /* fshto */ gen_vfp_shto(dp, 16 - rm, 0); break; Loading target/arm/vfp.decode +4 −0 Original line number Diff line number Diff line Loading @@ -220,3 +220,7 @@ VCVT_int_sp ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \ vd=%vd_sp vm=%vm_sp VCVT_int_dp ---- 1110 1.11 1000 .... 1011 s:1 1.0 .... \ vd=%vd_dp vm=%vm_sp # VJCVT is always dp to sp VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... \ vd=%vd_sp vm=%vm_dp Loading
target/arm/translate-vfp.inc.c +28 −0 Original line number Diff line number Diff line Loading @@ -2426,3 +2426,31 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a) tcg_temp_free_ptr(fpst); return true; } static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) { TCGv_i32 vd; TCGv_i64 vm; if (!dc_isar_feature(aa32_jscvt, s)) { return false; } /* UNDEF accesses to D16-D31 if they don't exist. */ if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { return false; } if (!vfp_access_check(s)) { return true; } vm = tcg_temp_new_i64(); vd = tcg_temp_new_i32(); neon_load_reg64(vm, a->vm); gen_helper_vjcvt(vd, vm, cpu_env); neon_store_reg32(vd, a->vd); tcg_temp_free_i64(vm); tcg_temp_free_i32(vd); return true; }
target/arm/translate.c +1 −11 Original line number Diff line number Diff line Loading @@ -3050,7 +3050,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) return 1; case 15: switch (rn) { case 0 ... 17: case 0 ... 19: /* Already handled by decodetree */ return 1; default: Loading Loading @@ -3085,13 +3085,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) rm_is_dp = false; break; case 0x13: /* vjcvt */ if (!dp || !dc_isar_feature(aa32_jscvt, s)) { return 1; } rd_is_dp = false; break; default: return 1; } Loading Loading @@ -3177,9 +3170,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) switch (op) { case 15: /* extension space */ switch (rn) { case 19: /* vjcvt */ gen_helper_vjcvt(cpu_F0s, cpu_F0d, cpu_env); break; case 20: /* fshto */ gen_vfp_shto(dp, 16 - rm, 0); break; Loading
target/arm/vfp.decode +4 −0 Original line number Diff line number Diff line Loading @@ -220,3 +220,7 @@ VCVT_int_sp ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \ vd=%vd_sp vm=%vm_sp VCVT_int_dp ---- 1110 1.11 1000 .... 1011 s:1 1.0 .... \ vd=%vd_dp vm=%vm_sp # VJCVT is always dp to sp VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... \ vd=%vd_sp vm=%vm_dp