Commit 8fc9d891 authored by Peter Maydell's avatar Peter Maydell
Browse files

target/arm: Convert integer-to-float insns to decodetree 



Convert the VCVT integer-to-float instructions to decodetree.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent 6ed7e49c

target/arm/translate-vfp.inc.c

+58 −0
Original line number Diff line number Diff line
@@ -2368,3 +2368,61 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a) 
    tcg_temp_free_i64(vm);

    return true;

}



static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)

{

    TCGv_i32 vm;

    TCGv_ptr fpst;



    if (!vfp_access_check(s)) {

        return true;

    }



    vm = tcg_temp_new_i32();

    neon_load_reg32(vm, a->vm);

    fpst = get_fpstatus_ptr(false);

    if (a->s) {

        /* i32 -> f32 */

        gen_helper_vfp_sitos(vm, vm, fpst);

    } else {

        /* u32 -> f32 */

        gen_helper_vfp_uitos(vm, vm, fpst);

    }

    neon_store_reg32(vm, a->vd);

    tcg_temp_free_i32(vm);

    tcg_temp_free_ptr(fpst);

    return true;

}



static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)

{

    TCGv_i32 vm;

    TCGv_i64 vd;

    TCGv_ptr fpst;



    /* UNDEF accesses to D16-D31 if they don't exist. */

    if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {

        return false;

    }



    if (!vfp_access_check(s)) {

        return true;

    }



    vm = tcg_temp_new_i32();

    vd = tcg_temp_new_i64();

    neon_load_reg32(vm, a->vm);

    fpst = get_fpstatus_ptr(false);

    if (a->s) {

        /* i32 -> f64 */

        gen_helper_vfp_sitod(vd, vm, fpst);

    } else {

        /* u32 -> f64 */

        gen_helper_vfp_uitod(vd, vm, fpst);

    }

    neon_store_reg64(vd, a->vd);

    tcg_temp_free_i32(vm);

    tcg_temp_free_i64(vd);

    tcg_temp_free_ptr(fpst);

    return true;

}

target/arm/translate.c

+1 −11
Original line number Diff line number Diff line
@@ -3050,7 +3050,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) 
                return 1;

            case 15:

                switch (rn) {

                case 0 ... 15:

                case 0 ... 17:

                    /* Already handled by decodetree */

                    return 1;

                default:
@@ -3063,10 +3063,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) 
            if (op == 15) {

                /* rn is opcode, encoded as per VFP_SREG_N. */

                switch (rn) {

                case 0x10: /* vcvt.fxx.u32 */

                case 0x11: /* vcvt.fxx.s32 */

                    rm_is_dp = false;

                    break;

                case 0x18: /* vcvtr.u32.fxx */

                case 0x19: /* vcvtz.u32.fxx */

                case 0x1a: /* vcvtr.s32.fxx */
@@ -3181,12 +3177,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) 
                switch (op) {

                case 15: /* extension space */

                    switch (rn) {

                    case 16: /* fuito */

                        gen_vfp_uito(dp, 0);

                        break;

                    case 17: /* fsito */

                        gen_vfp_sito(dp, 0);

                        break;

                    case 19: /* vjcvt */

                        gen_helper_vjcvt(cpu_F0s, cpu_F0d, cpu_env);

                        break;

target/arm/vfp.decode

+6 −0
Original line number Diff line number Diff line
@@ -214,3 +214,9 @@ VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... \ 
             vd=%vd_dp vm=%vm_sp

VCVT_dp      ---- 1110 1.11 0111 .... 1011 11.0 .... \

             vd=%vd_sp vm=%vm_dp



# VCVT from integer to floating point: Vm always single; Vd depends on size

VCVT_int_sp  ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \

             vd=%vd_sp vm=%vm_sp

VCVT_int_dp  ---- 1110 1.11 1000 .... 1011 s:1 1.0 .... \

             vd=%vd_dp vm=%vm_sp