Commit 8bebf7d1 authored by Richard Henderson's avatar Richard Henderson
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target/openrisc: Add VR2 and AVR special processor registers 



Update the CPUCFG bits to arch v1.3.
Include support for AVRP for cpu "any".

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent c7efab4f

target/openrisc/cpu.c

+6 −2
Original line number Diff line number Diff line
@@ -126,9 +126,13 @@ static void openrisc_any_initfn(Object *obj) 
{

    OpenRISCCPU *cpu = OPENRISC_CPU(obj);



    cpu->env.vr = 0x13000000;

    cpu->env.vr = 0x13000040;   /* Obsolete VER + UVRP for new SPRs */

    cpu->env.vr2 = 0;           /* No version specific id */

    cpu->env.avr = 0x01010000;  /* Architecture v1.1 */



    cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;

    cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP;

    cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S |

                       CPUCFGR_AVRP | CPUCFGR_EVBARP;



    /* 1Way, TLB_SIZE entries.  */

    cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))

target/openrisc/cpu.h

+7 −4
Original line number Diff line number Diff line
@@ -96,11 +96,12 @@ enum { 
    CPUCFGR_OF32S = (1 << 7),

    CPUCFGR_OF64S = (1 << 8),

    CPUCFGR_OV64S = (1 << 9),

    /* CPUCFGR_ND = (1 << 10), */

    /* CPUCFGR_AVRP = (1 << 11), */

    CPUCFGR_ND = (1 << 10),

    CPUCFGR_AVRP = (1 << 11),

    CPUCFGR_EVBARP = (1 << 12),

    /* CPUCFGR_ISRP = (1 << 13), */

    /* CPUCFGR_AECSRP = (1 << 14), */

    CPUCFGR_ISRP = (1 << 13),

    CPUCFGR_AECSRP = (1 << 14),

    CPUCFGR_OF64A32S = (1 << 15),

};



/* DMMU configure register */
@@ -280,6 +281,8 @@ typedef struct CPUOpenRISCState { 


    /* Fields from here on are preserved across CPU reset. */

    uint32_t vr;              /* Version register */

    uint32_t vr2;             /* Version register 2 */

    uint32_t avr;             /* Architecture version register */

    uint32_t upr;             /* Unit presence register */

    uint32_t cpucfgr;         /* CPU configure register */

    uint32_t dmmucfgr;        /* DMMU configure register */

target/openrisc/sys_helper.c

+6 −0
Original line number Diff line number Diff line
@@ -210,6 +210,12 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, 
    case TO_SPR(0, 4): /* IMMUCFGR */

        return env->immucfgr;



    case TO_SPR(0, 9): /* VR2 */

        return env->vr2;



    case TO_SPR(0, 10): /* AVR */

        return env->avr;



    case TO_SPR(0, 11): /* EVBAR */

        return env->evbar;