Commit 8b3e9ca7 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/rth/tags/pull-s390-20170606' into staging 



Queued s390 patches

# gpg: Signature made Wed 07 Jun 2017 01:18:29 BST
# gpg:                using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg:                 aka "Richard Henderson <rth@redhat.com>"
# gpg:                 aka "Richard Henderson <rth@twiddle.net>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC  16A4 AD12 70CC 4DD0 279B

* remotes/rth/tags/pull-s390-20170606: (70 commits)
  target/s390x: addressing exceptions are suppressing
  target/s390x: mark ETF2 and ETF2-ENH facilities as available
  target/s390x: check alignment in CDSG in the !CONFIG_ATOMIC128 case
  target/s390x: implement STORE PAIR TO QUADWORD
  target/s390x: implement LOAD PAIR FROM QUADWORD
  target/s390x: implement TRANSLATE ONE/TWO TO ONE/TWO
  target/s390x: implement TEST DECIMAL
  target/s390x: implement UNPACK UNICODE
  target/s390x: implement UNPACK ASCII
  target/s390x: implement PACK UNICODE
  target/s390x: implement PACK ASCII
  target/s390x: implement MOVE LONG UNICODE
  target/s390x: implement COMPARE LOGICAL LONG UNICODE
  target/s390x: improve MOVE LONG and MOVE LONG EXTENDED
  target/s390x: fix adj_len_to_page
  target/s390x: implement COMPARE LOGICAL LONG
  target/s390x: fix COMPARE LOGICAL LONG EXTENDED
  target/s390x: improve 24-bit and 31-bit lengths read/write
  target/s390x: improve 24-bit and 31-bit addresses write
  target/s390x: improve 24-bit and 31-bit addresses read
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 65dfad62 49921d68

target/s390x/cpu.h

+6 −1
Original line number Diff line number Diff line
@@ -107,6 +107,8 @@ typedef struct CPUS390XState { 
    uint64_t cc_dst;

    uint64_t cc_vr;



    uint64_t ex_value;



    uint64_t __excp_addr;

    uint64_t psa;
@@ -393,7 +395,7 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, 
                                        target_ulong *cs_base, uint32_t *flags)

{

    *pc = env->psw.addr;

    *cs_base = 0;

    *cs_base = env->ex_value;

    *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |

             ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);

}
@@ -1033,6 +1035,8 @@ struct sysib_322 { 
#define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */

#define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */



#define VADDR_PX                0xff000   /* page index bits                  */



#define _PAGE_RO        0x200            /* HW read-only bit  */

#define _PAGE_INVALID   0x400            /* HW invalid bit    */

#define _PAGE_RES0      0x800            /* bit must be zero  */
@@ -1084,6 +1088,7 @@ struct sysib_322 { 
#define SIGP_ORDER_MASK 0x000000ff



void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);

target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr);

int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,

                  target_ulong *raddr, int *flags, bool exc);

int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);

target/s390x/cpu_models.c

+33 −3
Original line number Diff line number Diff line
@@ -658,6 +658,32 @@ static void check_compatibility(const S390CPUModel *max_model, 
                  "available in the configuration: ");

}



/**

 * The base TCG CPU model "qemu" is based on the z900. However, we already

 * can also emulate some additional features of later CPU generations, so

 * we add these additional feature bits here.

 */

static void add_qemu_cpu_model_features(S390FeatBitmap fbm)

{

    static const int feats[] = {

        S390_FEAT_STFLE,

        S390_FEAT_EXTENDED_IMMEDIATE,

        S390_FEAT_EXTENDED_TRANSLATION_2,

        S390_FEAT_LONG_DISPLACEMENT,

        S390_FEAT_LONG_DISPLACEMENT_FAST,

        S390_FEAT_ETF2_ENH,

        S390_FEAT_STORE_CLOCK_FAST,

        S390_FEAT_GENERAL_INSTRUCTIONS_EXT,

        S390_FEAT_EXECUTE_EXT,

        S390_FEAT_STFLE_45,

    };

    int i;



    for (i = 0; i < ARRAY_SIZE(feats); i++) {

        set_bit(feats[i], fbm);

    }

}



static S390CPUModel *get_max_cpu_model(Error **errp)

{

    static S390CPUModel max_model;
@@ -670,10 +696,11 @@ static S390CPUModel *get_max_cpu_model(Error **errp) 
    if (kvm_enabled()) {

        kvm_s390_get_host_cpu_model(&max_model, errp);

    } else {

        /* TCG emulates a z900 */

        /* TCG emulates a z900 (with some optional additional features) */

        max_model.def = &s390_cpu_defs[0];

        bitmap_copy(max_model.features, max_model.def->default_feat,

                    S390_FEAT_MAX);

        add_qemu_cpu_model_features(max_model.features);

    }

    if (!*errp) {

        cached = true;
@@ -925,11 +952,14 @@ static void s390_host_cpu_model_initfn(Object *obj) 


static void s390_qemu_cpu_model_initfn(Object *obj)

{

    static S390CPUDef s390_qemu_cpu_defs;

    S390CPU *cpu = S390_CPU(obj);



    cpu->model = g_malloc0(sizeof(*cpu->model));

    /* TCG emulates a z900 */

    cpu->model->def = &s390_cpu_defs[0];

    /* TCG emulates a z900 (with some optional additional features) */

    memcpy(&s390_qemu_cpu_defs, &s390_cpu_defs[0], sizeof(s390_qemu_cpu_defs));

    add_qemu_cpu_model_features(s390_qemu_cpu_defs.full_feat);

    cpu->model->def = &s390_qemu_cpu_defs;

    bitmap_copy(cpu->model->features, cpu->model->def->default_feat,

                S390_FEAT_MAX);

}

target/s390x/fpu_helper.c

+27 −0
Original line number Diff line number Diff line
@@ -585,6 +585,33 @@ uint64_t HELPER(fixb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint32_t m3) 
    return RET128(ret);

}



/* 32-bit FP compare and signal */

uint32_t HELPER(keb)(CPUS390XState *env, uint64_t f1, uint64_t f2)

{

    int cmp = float32_compare(f1, f2, &env->fpu_status);

    handle_exceptions(env, GETPC());

    return float_comp_to_cc(env, cmp);

}



/* 64-bit FP compare and signal */

uint32_t HELPER(kdb)(CPUS390XState *env, uint64_t f1, uint64_t f2)

{

    int cmp = float64_compare(f1, f2, &env->fpu_status);

    handle_exceptions(env, GETPC());

    return float_comp_to_cc(env, cmp);

}



/* 128-bit FP compare and signal */

uint32_t HELPER(kxb)(CPUS390XState *env, uint64_t ah, uint64_t al,

                     uint64_t bh, uint64_t bl)

{

    int cmp = float128_compare(make_float128(ah, al),

                               make_float128(bh, bl),

                               &env->fpu_status);

    handle_exceptions(env, GETPC());

    return float_comp_to_cc(env, cmp);

}



/* 32-bit FP multiply and add */

uint64_t HELPER(maeb)(CPUS390XState *env, uint64_t f1,

                      uint64_t f2, uint64_t f3)

target/s390x/helper.c

+6 −1
Original line number Diff line number Diff line
@@ -204,7 +204,7 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, 
    if (raddr > ram_size) {

        DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,

                (uint64_t)raddr, (uint64_t)ram_size);

        trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_LATER);

        trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_LATER_INC);

        return 1;

    }
@@ -642,6 +642,11 @@ bool s390_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 
        S390CPU *cpu = S390_CPU(cs);

        CPUS390XState *env = &cpu->env;



        if (env->ex_value) {

            /* Execution of the target insn is indivisible from

               the parent EXECUTE insn.  */

            return false;

        }

        if (env->psw.mask & PSW_MASK_EXT) {

            s390_cpu_do_interrupt(cs);

            return true;

target/s390x/helper.h

+24 −4
Original line number Diff line number Diff line
@@ -3,8 +3,10 @@ DEF_HELPER_FLAGS_4(nc, TCG_CALL_NO_WG, i32, env, i32, i64, i64) 
DEF_HELPER_FLAGS_4(oc, TCG_CALL_NO_WG, i32, env, i32, i64, i64)

DEF_HELPER_FLAGS_4(xc, TCG_CALL_NO_WG, i32, env, i32, i64, i64)

DEF_HELPER_FLAGS_4(mvc, TCG_CALL_NO_WG, void, env, i32, i64, i64)

DEF_HELPER_FLAGS_4(mvcin, TCG_CALL_NO_WG, void, env, i32, i64, i64)

DEF_HELPER_FLAGS_4(clc, TCG_CALL_NO_WG, i32, env, i32, i64, i64)

DEF_HELPER_3(mvcl, i32, env, i32, i32)

DEF_HELPER_3(clcl, i32, env, i32, i32)

DEF_HELPER_FLAGS_4(clm, TCG_CALL_NO_WG, i32, env, i32, i32, i64)

DEF_HELPER_FLAGS_3(divs32, TCG_CALL_NO_WG, s64, env, s64, s64)

DEF_HELPER_FLAGS_3(divu32, TCG_CALL_NO_WG, i64, env, i64, i64)
@@ -12,13 +14,18 @@ DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, s64, env, s64, s64) 
DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i64, env, i64, i64, i64)

DEF_HELPER_4(srst, i64, env, i64, i64, i64)

DEF_HELPER_4(clst, i64, env, i64, i64, i64)

DEF_HELPER_4(mvpg, void, env, i64, i64, i64)

DEF_HELPER_FLAGS_4(mvn, TCG_CALL_NO_WG, void, env, i32, i64, i64)

DEF_HELPER_FLAGS_4(mvo, TCG_CALL_NO_WG, void, env, i32, i64, i64)

DEF_HELPER_FLAGS_4(mvpg, TCG_CALL_NO_WG, i32, env, i64, i64, i64)

DEF_HELPER_FLAGS_4(mvz, TCG_CALL_NO_WG, void, env, i32, i64, i64)

DEF_HELPER_4(mvst, i64, env, i64, i64, i64)

DEF_HELPER_5(ex, i32, env, i32, i64, i64, i64)

DEF_HELPER_4(ex, void, env, i32, i64, i64)

DEF_HELPER_FLAGS_4(stam, TCG_CALL_NO_WG, void, env, i32, i64, i32)

DEF_HELPER_FLAGS_4(lam, TCG_CALL_NO_WG, void, env, i32, i64, i32)

DEF_HELPER_4(mvcle, i32, env, i32, i64, i32)

DEF_HELPER_4(mvclu, i32, env, i32, i64, i32)

DEF_HELPER_4(clcle, i32, env, i32, i64, i32)

DEF_HELPER_4(clclu, i32, env, i32, i64, i32)

DEF_HELPER_3(cegb, i64, env, s64, i32)

DEF_HELPER_3(cdgb, i64, env, s64, i32)

DEF_HELPER_3(cxgb, i64, env, s64, i32)
@@ -49,6 +56,9 @@ DEF_HELPER_FLAGS_3(lexb, TCG_CALL_NO_WG, i64, env, i64, i64) 
DEF_HELPER_FLAGS_3(ceb, TCG_CALL_NO_WG_SE, i32, env, i64, i64)

DEF_HELPER_FLAGS_3(cdb, TCG_CALL_NO_WG_SE, i32, env, i64, i64)

DEF_HELPER_FLAGS_5(cxb, TCG_CALL_NO_WG_SE, i32, env, i64, i64, i64, i64)

DEF_HELPER_FLAGS_3(keb, TCG_CALL_NO_WG, i32, env, i64, i64)

DEF_HELPER_FLAGS_3(kdb, TCG_CALL_NO_WG, i32, env, i64, i64)

DEF_HELPER_FLAGS_5(kxb, TCG_CALL_NO_WG, i32, env, i64, i64, i64, i64)

DEF_HELPER_FLAGS_3(cgeb, TCG_CALL_NO_WG, i64, env, i64, i32)

DEF_HELPER_FLAGS_3(cgdb, TCG_CALL_NO_WG, i64, env, i64, i32)

DEF_HELPER_FLAGS_4(cgxb, TCG_CALL_NO_WG, i64, env, i64, i64, i32)
@@ -75,10 +85,17 @@ DEF_HELPER_FLAGS_2(sqeb, TCG_CALL_NO_WG, i64, env, i64) 
DEF_HELPER_FLAGS_2(sqdb, TCG_CALL_NO_WG, i64, env, i64)

DEF_HELPER_FLAGS_3(sqxb, TCG_CALL_NO_WG, i64, env, i64, i64)

DEF_HELPER_FLAGS_1(cvd, TCG_CALL_NO_RWG_SE, i64, s32)

DEF_HELPER_FLAGS_4(pack, TCG_CALL_NO_WG, void, env, i32, i64, i64)

DEF_HELPER_FLAGS_4(pka, TCG_CALL_NO_WG, void, env, i64, i64, i32)

DEF_HELPER_FLAGS_4(pku, TCG_CALL_NO_WG, void, env, i64, i64, i32)

DEF_HELPER_FLAGS_4(unpk, TCG_CALL_NO_WG, void, env, i32, i64, i64)

DEF_HELPER_FLAGS_4(unpka, TCG_CALL_NO_WG, i32, env, i64, i32, i64)

DEF_HELPER_FLAGS_4(unpku, TCG_CALL_NO_WG, i32, env, i64, i32, i64)

DEF_HELPER_FLAGS_3(tp, TCG_CALL_NO_WG, i32, env, i64, i32)

DEF_HELPER_FLAGS_4(tr, TCG_CALL_NO_WG, void, env, i32, i64, i64)

DEF_HELPER_4(tre, i64, env, i64, i64, i64)

DEF_HELPER_4(trt, i32, env, i32, i64, i64)

DEF_HELPER_5(trXX, i32, env, i32, i32, i32, i32)

DEF_HELPER_4(cksm, i64, env, i64, i64, i64)

DEF_HELPER_FLAGS_5(calc_cc, TCG_CALL_NO_RWG_SE, i32, env, i32, i64, i64, i64)

DEF_HELPER_FLAGS_2(sfpc, TCG_CALL_NO_RWG, void, env, i64)
@@ -86,6 +103,8 @@ DEF_HELPER_FLAGS_2(sfas, TCG_CALL_NO_WG, void, env, i64) 
DEF_HELPER_FLAGS_1(popcnt, TCG_CALL_NO_RWG_SE, i64, i64)

DEF_HELPER_FLAGS_1(stfl, TCG_CALL_NO_RWG, void, env)

DEF_HELPER_2(stfle, i32, env, i64)

DEF_HELPER_FLAGS_2(lpq, TCG_CALL_NO_WG, i64, env, i64)

DEF_HELPER_FLAGS_4(stpq, TCG_CALL_NO_WG, void, env, i64, i64, i64)



#ifndef CONFIG_USER_ONLY

DEF_HELPER_3(servc, i32, env, i64, i64)
@@ -102,17 +121,18 @@ DEF_HELPER_FLAGS_4(lctl, TCG_CALL_NO_WG, void, env, i32, i64, i32) 
DEF_HELPER_FLAGS_4(lctlg, TCG_CALL_NO_WG, void, env, i32, i64, i32)

DEF_HELPER_FLAGS_4(stctl, TCG_CALL_NO_WG, void, env, i32, i64, i32)

DEF_HELPER_FLAGS_4(stctg, TCG_CALL_NO_WG, void, env, i32, i64, i32)

DEF_HELPER_FLAGS_2(testblock, TCG_CALL_NO_WG, i32, env, i64)

DEF_HELPER_FLAGS_2(tprot, TCG_CALL_NO_RWG, i32, i64, i64)

DEF_HELPER_FLAGS_2(iske, TCG_CALL_NO_RWG_SE, i64, env, i64)

DEF_HELPER_FLAGS_3(sske, TCG_CALL_NO_RWG, void, env, i64, i64)

DEF_HELPER_FLAGS_2(rrbe, TCG_CALL_NO_RWG, i32, env, i64)

DEF_HELPER_3(csp, i32, env, i32, i64)

DEF_HELPER_4(mvcs, i32, env, i64, i64, i64)

DEF_HELPER_4(mvcp, i32, env, i64, i64, i64)

DEF_HELPER_4(sigp, i32, env, i64, i32, i64)

DEF_HELPER_FLAGS_2(sacf, TCG_CALL_NO_WG, void, env, i64)

DEF_HELPER_FLAGS_3(ipte, TCG_CALL_NO_RWG, void, env, i64, i64)

DEF_HELPER_FLAGS_4(ipte, TCG_CALL_NO_RWG, void, env, i64, i64, i32)

DEF_HELPER_FLAGS_1(ptlb, TCG_CALL_NO_RWG, void, env)

DEF_HELPER_FLAGS_1(purge, TCG_CALL_NO_RWG, void, env)

DEF_HELPER_2(lra, i64, env, i64)

DEF_HELPER_FLAGS_2(lura, TCG_CALL_NO_WG, i64, env, i64)

DEF_HELPER_FLAGS_2(lurag, TCG_CALL_NO_WG, i64, env, i64)