Commit 86cf1e9f authored by Suraj Jitindar Singh's avatar Suraj Jitindar Singh Committed by David Gibson
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target/ppc/POWER9: Add ISAv3.00 MMU definition 



POWER9 processors implement the mmu as defined in version 3.00 of the ISA.

Add a definition for this mmu model and set the POWER9 cpu model to use
this mmu model.

Signed-off-by: default avatarSuraj Jitindar Singh <sjitindarsingh@gmail.com>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent 7659ca1a

target/ppc/cpu-qom.h

+4 −1
Original line number Diff line number Diff line
@@ -86,10 +86,13 @@ enum powerpc_mmu_t { 
    POWERPC_MMU_2_07       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG

                             | POWERPC_MMU_64K

                             | POWERPC_MMU_AMR | 0x00000004,

    /* FIXME Add POWERPC_MMU_3_OO defines */

    /* Architecture 2.07 "degraded" (no 1T segments)           */

    POWERPC_MMU_2_07a      = POWERPC_MMU_64 | POWERPC_MMU_AMR

                             | 0x00000004,

    /* Architecture 3.00 variant                               */

    POWERPC_MMU_3_00       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG

                             | POWERPC_MMU_64K

                             | POWERPC_MMU_AMR | 0x00000005,

};



/*****************************************************************************/

target/ppc/mmu_helper.c

+2 −0
Original line number Diff line number Diff line
@@ -1935,6 +1935,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) 
    case POWERPC_MMU_2_06a:

    case POWERPC_MMU_2_07:

    case POWERPC_MMU_2_07a:

    case POWERPC_MMU_3_00:

#endif /* defined(TARGET_PPC64) */

        env->tlb_need_flush = 0;

        tlb_flush(CPU(cpu));
@@ -1974,6 +1975,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) 
    case POWERPC_MMU_2_06a:

    case POWERPC_MMU_2_07:

    case POWERPC_MMU_2_07a:

    case POWERPC_MMU_3_00:

        /* tlbie invalidate TLBs for all segments */

        /* XXX: given the fact that there are too many segments to invalidate,

         *      and we still don't have a tlb_flush_mask(env, n, mask) in QEMU,

target/ppc/translate_init.c

+1 −2
Original line number Diff line number Diff line
@@ -8816,8 +8816,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 
                    (1ull << MSR_PMM) |

                    (1ull << MSR_RI) |

                    (1ull << MSR_LE);

    /* Using 2.07 defines until new radix model is added. */

    pcc->mmu_model = POWERPC_MMU_2_07;

    pcc->mmu_model = POWERPC_MMU_3_00;

#if defined(CONFIG_SOFTMMU)

    pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;

    /* segment page size remain the same */