Commit 7659ca1a authored by Suraj Jitindar Singh's avatar Suraj Jitindar Singh Committed by David Gibson
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target/ppc: Fix LPCR DPFD mask define 



The DPFD field in the LPCR is 3 bits wide. This has always been defined
as 0x3 << shift which indicates a 2 bit field, which is incorrect.
Correct this.

Signed-off-by: default avatarSuraj Jitindar Singh <sjitindarsingh@gmail.com>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent e0aee726

target/ppc/cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -381,7 +381,7 @@ struct ppc_slb_t { 
#define LPCR_ISL          (1ull << (63 - 2))

#define LPCR_KBV          (1ull << (63 - 3))

#define LPCR_DPFD_SHIFT   (63 - 11)

#define LPCR_DPFD         (0x3ull << LPCR_DPFD_SHIFT)

#define LPCR_DPFD         (0x7ull << LPCR_DPFD_SHIFT)

#define LPCR_VRMASD_SHIFT (63 - 16)

#define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT)

#define LPCR_RMLS_SHIFT   (63 - 37)