Commit 834a6c69 authored by Peter Maydell's avatar Peter Maydell
Browse files

target-arm: Implement missing ACTLR registers 



We already implemented ACTLR_EL1; add the missing ACTLR_EL2 and
ACTLR_EL3, for consistency.

Since we don't currently have any CPUs that need the EL2/EL3
versions to reset to non-zero values, implement as RAZ/WI.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1438281398-18746-5-git-send-email-peter.maydell@linaro.org
parent 37cd6c24

target-arm/helper.c

+15 −6
Original line number Diff line number Diff line
@@ -3936,13 +3936,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) 
    }



    if (arm_feature(env, ARM_FEATURE_AUXCR)) {

        ARMCPRegInfo auxcr = {

            .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,

        ARMCPRegInfo auxcr_reginfo[] = {

            { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,

              .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,

              .access = PL1_RW, .type = ARM_CP_CONST,

            .resetvalue = cpu->reset_auxcr

              .resetvalue = cpu->reset_auxcr },

            { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,

              .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,

              .access = PL2_RW, .type = ARM_CP_CONST,

              .resetvalue = 0 },

            { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,

              .access = PL3_RW, .type = ARM_CP_CONST,

              .resetvalue = 0 },

            REGINFO_SENTINEL

        };

        define_one_arm_cp_reg(cpu, &auxcr);

        define_arm_cp_regs(cpu, auxcr_reginfo);

    }



    if (arm_feature(env, ARM_FEATURE_CBAR)) {