Commit 37cd6c24 authored by Peter Maydell's avatar Peter Maydell
Browse files

target-arm: Implement missing AFSR registers 



The AFSR registers are implementation dependent auxiliary fault
status registers. We already implemented a RAZ/WI AFSR0_EL1 and
AFSR_EL1; add the missing AFSR{0,1}_EL{2,3} for consistency.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1438281398-18746-4-git-send-email-peter.maydell@linaro.org
parent 2179ef95

target-arm/helper.c

+24 −0
Original line number Diff line number Diff line
@@ -2848,6 +2848,14 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { 
      .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,

      .access = PL2_RW, .type = ARM_CP_CONST,

      .resetvalue = 0 },

    { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,

      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,

      .access = PL2_RW, .type = ARM_CP_CONST,

      .resetvalue = 0 },

    { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,

      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,

      .access = PL2_RW, .type = ARM_CP_CONST,

      .resetvalue = 0 },

    { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,

      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,

      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -2972,6 +2980,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { 
      .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,

      .access = PL2_RW, .type = ARM_CP_CONST,

      .resetvalue = 0 },

    { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,

      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,

      .access = PL2_RW, .type = ARM_CP_CONST,

      .resetvalue = 0 },

    { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,

      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,

      .access = PL2_RW, .type = ARM_CP_CONST,

      .resetvalue = 0 },

    { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,

      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,

      .access = PL2_RW, .writefn = vmsa_tcr_el1_write,
@@ -3118,6 +3134,14 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { 
      .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,

      .access = PL3_RW, .type = ARM_CP_CONST,

      .resetvalue = 0 },

    { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,

      .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,

      .access = PL3_RW, .type = ARM_CP_CONST,

      .resetvalue = 0 },

    { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,

      .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,

      .access = PL3_RW, .type = ARM_CP_CONST,

      .resetvalue = 0 },

    REGINFO_SENTINEL

};