Unverified Commit 81e94379 authored by Bin Meng's avatar Bin Meng Committed by Palmer Dabbelt
Browse files

riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet 



In the past we did not have a model for PRCI, hence two handcrafted
clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the
purpose of supplying hard-coded clock frequencies. But now since we
have added the PRCI support in QEMU, we don't need them any more.

Signed-off-by: default avatarBin Meng <bmeng.cn@gmail.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent 7b6bb66f

hw/riscv/sifive_u.c

+1 −23
Original line number Diff line number Diff line
@@ -87,8 +87,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 
    uint32_t *cells;

    char *nodename;

    char ethclk_names[] = "pclk\0hclk";

    uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1;

    uint32_t uartclk_phandle;

    uint32_t plic_phandle, prci_phandle, phandle = 1;

    uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;



    fdt = s->fdt = create_device_tree(&s->fdt_size);
@@ -248,17 +247,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 
    g_free(cells);

    g_free(nodename);



    ethclk_phandle = phandle++;

    nodename = g_strdup_printf("/soc/ethclk");

    qemu_fdt_add_subnode(fdt, nodename);

    qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");

    qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);

    qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",

        SIFIVE_U_GEM_CLOCK_FREQ);

    qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle);

    ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename);

    g_free(nodename);



    phy_phandle = phandle++;

    nodename = g_strdup_printf("/soc/ethernet@%lx",

        (long)memmap[SIFIVE_U_GEM].base);
@@ -292,16 +280,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 
    qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);

    g_free(nodename);



    uartclk_phandle = phandle++;

    nodename = g_strdup_printf("/soc/uartclk");

    qemu_fdt_add_subnode(fdt, nodename);

    qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");

    qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);

    qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);

    qemu_fdt_setprop_cell(fdt, nodename, "phandle", uartclk_phandle);

    uartclk_phandle = qemu_fdt_get_phandle(fdt, nodename);

    g_free(nodename);



    nodename = g_strdup_printf("/soc/serial@%lx",

        (long)memmap[SIFIVE_U_UART0].base);

    qemu_fdt_add_subnode(fdt, nodename);

include/hw/riscv/sifive_u.h

+1 −2
Original line number Diff line number Diff line
@@ -77,8 +77,7 @@ enum { 
enum {

    SIFIVE_U_CLOCK_FREQ = 1000000000,

    SIFIVE_U_HFCLK_FREQ = 33333333,

    SIFIVE_U_RTCCLK_FREQ = 1000000,

    SIFIVE_U_GEM_CLOCK_FREQ = 125000000

    SIFIVE_U_RTCCLK_FREQ = 1000000

};



#define SIFIVE_U_MANAGEMENT_CPU_COUNT   1