Unverified Commit 7b6bb66f authored by Bin Meng's avatar Bin Meng Committed by Palmer Dabbelt
Browse files

riscv: sifive_u: Fix broken GEM support 



At present the GEM support in sifive_u machine is seriously broken.
The GEM block register base was set to a weird number (0x100900FC),
which for no way could work with the cadence_gem model in QEMU.

Not like other GEM variants, the FU540-specific GEM has a management
block to control 10/100/1000Mbps link speed changes, that is mapped
to 0x100a0000. We can simply map it into MMIO space without special
handling using create_unimplemented_device().

Update the GEM node compatible string to use the official name used
by the upstream Linux kernel, and add the management block reg base
& size to the <reg> property encoding.

Tested with upstream U-Boot and Linux kernel MACB drivers.

Signed-off-by: default avatarBin Meng <bmeng.cn@gmail.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent 5461c4fe

hw/riscv/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ config SIFIVE_U 
    select CADENCE

    select HART

    select SIFIVE

    select UNIMP



config SPIKE

    bool

hw/riscv/sifive_u.c

+20 −4
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 *

 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu

 * Copyright (c) 2017 SiFive, Inc.

 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>

 *

 * Provides a board compatible with the SiFive Freedom U SDK:

 *
@@ -11,6 +12,7 @@ 
 * 2) PLIC (Platform Level Interrupt Controller)

 * 3) PRCI (Power, Reset, Clock, Interrupt)

 * 4) OTP (One-Time Programmable) memory with stored serial number

 * 5) GEM (Gigabit Ethernet Controller) and management block

 *

 * This board currently generates devicetree dynamically that indicates at least

 * two harts and up to five harts.
@@ -37,6 +39,7 @@ 
#include "hw/sysbus.h"

#include "hw/char/serial.h"

#include "hw/cpu/cluster.h"

#include "hw/misc/unimp.h"

#include "target/riscv/cpu.h"

#include "hw/riscv/riscv_hart.h"

#include "hw/riscv/sifive_plic.h"
@@ -45,6 +48,7 @@ 
#include "hw/riscv/sifive_u.h"

#include "hw/riscv/boot.h"

#include "chardev/char.h"

#include "net/eth.h"

#include "sysemu/arch_init.h"

#include "sysemu/device_tree.h"

#include "sysemu/sysemu.h"
@@ -67,7 +71,8 @@ static const struct MemmapEntry { 
    [SIFIVE_U_UART1] =    { 0x10011000,     0x1000 },

    [SIFIVE_U_OTP] =      { 0x10070000,     0x1000 },

    [SIFIVE_U_DRAM] =     { 0x80000000,        0x0 },

    [SIFIVE_U_GEM] =      { 0x100900FC,     0x2000 },

    [SIFIVE_U_GEM] =      { 0x10090000,     0x2000 },

    [SIFIVE_U_GEM_MGMT] = { 0x100a0000,     0x1000 },

};



#define OTP_SERIAL          1
@@ -84,7 +89,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 
    char ethclk_names[] = "pclk\0hclk";

    uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1;

    uint32_t uartclk_phandle;

    uint32_t hfclk_phandle, rtcclk_phandle;

    uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;



    fdt = s->fdt = create_device_tree(&s->fdt_size);

    if (!fdt) {
@@ -254,21 +259,28 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 
    ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename);

    g_free(nodename);



    phy_phandle = phandle++;

    nodename = g_strdup_printf("/soc/ethernet@%lx",

        (long)memmap[SIFIVE_U_GEM].base);

    qemu_fdt_add_subnode(fdt, nodename);

    qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb");

    qemu_fdt_setprop_string(fdt, nodename, "compatible",

        "sifive,fu540-c000-gem");

    qemu_fdt_setprop_cells(fdt, nodename, "reg",

        0x0, memmap[SIFIVE_U_GEM].base,

        0x0, memmap[SIFIVE_U_GEM].size);

        0x0, memmap[SIFIVE_U_GEM].size,

        0x0, memmap[SIFIVE_U_GEM_MGMT].base,

        0x0, memmap[SIFIVE_U_GEM_MGMT].size);

    qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");

    qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");

    qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);

    qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);

    qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);

    qemu_fdt_setprop_cells(fdt, nodename, "clocks",

        prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);

    qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,

        sizeof(ethclk_names));

    qemu_fdt_setprop(fdt, nodename, "local-mac-address",

        s->soc.gem.conf.macaddr.a, ETH_ALEN);

    qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);

    qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);

    g_free(nodename);
@@ -276,6 +288,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 
    nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",

        (long)memmap[SIFIVE_U_GEM].base);

    qemu_fdt_add_subnode(fdt, nodename);

    qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);

    qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);

    g_free(nodename);
@@ -525,6 +538,9 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) 
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,

                       plic_gpios[SIFIVE_U_GEM_IRQ]);



    create_unimplemented_device("riscv.sifive.u.gem-mgmt",

        memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);

}



static void riscv_sifive_u_machine_init(MachineClass *mc)

include/hw/riscv/sifive_u.h

+2 −1
Original line number Diff line number Diff line
@@ -64,7 +64,8 @@ enum { 
    SIFIVE_U_UART1,

    SIFIVE_U_OTP,

    SIFIVE_U_DRAM,

    SIFIVE_U_GEM

    SIFIVE_U_GEM,

    SIFIVE_U_GEM_MGMT

};



enum {