Unverified Commit 5461c4fe authored by Bin Meng's avatar Bin Meng Committed by Palmer Dabbelt
Browse files

riscv: sifive_u: Instantiate OTP memory with a serial number 



This adds an OTP memory with a given serial number to the sifive_u
machine. With such support, the upstream U-Boot for sifive_fu540
boots out of the box on the sifive_u machine.

Signed-off-by: default avatarBin Meng <bmeng.cn@gmail.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent 9fb45c62

hw/riscv/sifive_u.c

+9 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
 * 1) CLINT (Core Level Interruptor)

 * 2) PLIC (Platform Level Interrupt Controller)

 * 3) PRCI (Power, Reset, Clock, Interrupt)

 * 4) OTP (One-Time Programmable) memory with stored serial number

 *

 * This board currently generates devicetree dynamically that indicates at least

 * two harts and up to five harts.
@@ -64,10 +65,12 @@ static const struct MemmapEntry { 
    [SIFIVE_U_PRCI] =     { 0x10000000,     0x1000 },

    [SIFIVE_U_UART0] =    { 0x10010000,     0x1000 },

    [SIFIVE_U_UART1] =    { 0x10011000,     0x1000 },

    [SIFIVE_U_OTP] =      { 0x10070000,     0x1000 },

    [SIFIVE_U_DRAM] =     { 0x80000000,        0x0 },

    [SIFIVE_U_GEM] =      { 0x100900FC,     0x2000 },

};



#define OTP_SERIAL          1

#define GEM_REVISION        0x10070109



static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
@@ -422,6 +425,9 @@ static void riscv_sifive_u_soc_init(Object *obj) 


    sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci),

                          TYPE_SIFIVE_U_PRCI);

    sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),

                          TYPE_SIFIVE_U_OTP);

    qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL);

    sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),

                          TYPE_CADENCE_GEM);

}
@@ -498,6 +504,9 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) 
    object_property_set_bool(OBJECT(&s->prci), true, "realized", &err);

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);



    object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);



    for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {

        plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);

    }

include/hw/riscv/sifive_u.h

+3 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
#include "hw/riscv/riscv_hart.h"

#include "hw/riscv/sifive_cpu.h"

#include "hw/riscv/sifive_u_prci.h"

#include "hw/riscv/sifive_u_otp.h"



#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"

#define RISCV_U_SOC(obj) \
@@ -39,6 +40,7 @@ typedef struct SiFiveUSoCState { 
    RISCVHartArrayState u_cpus;

    DeviceState *plic;

    SiFiveUPRCIState prci;

    SiFiveUOTPState otp;

    CadenceGEMState gem;

} SiFiveUSoCState;
@@ -60,6 +62,7 @@ enum { 
    SIFIVE_U_PRCI,

    SIFIVE_U_UART0,

    SIFIVE_U_UART1,

    SIFIVE_U_OTP,

    SIFIVE_U_DRAM,

    SIFIVE_U_GEM

};