Commit 817a1cec authored by David Hildenbrand's avatar David Hildenbrand
Browse files

s390x/tcg: Implement VECTOR FP DIVIDE 



We can reuse most of the infrastructure added for VECTOR FP ADD.

Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: default avatarDavid Hildenbrand <david@redhat.com>
parent 09c04e4b

target/s390x/helper.h

+2 −0
Original line number Diff line number Diff line
@@ -274,6 +274,8 @@ DEF_HELPER_FLAGS_4(gvec_vcgd64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) 
DEF_HELPER_FLAGS_4(gvec_vcgd64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)

DEF_HELPER_FLAGS_4(gvec_vclgd64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)

DEF_HELPER_FLAGS_4(gvec_vclgd64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)

DEF_HELPER_FLAGS_5(gvec_vfd64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)

DEF_HELPER_FLAGS_5(gvec_vfd64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)



#ifndef CONFIG_USER_ONLY

DEF_HELPER_3(servc, i32, env, i64, i64)

target/s390x/insn-data.def

+2 −0
Original line number Diff line number Diff line
@@ -1226,6 +1226,8 @@ 
    F(0xe7c2, VCGD,    VRR_a, V,   0, 0, 0, 0, vcdg, 0, IF_VEC)

/* VECTOR FP CONVERT TO LOGICAL 64-BIT */

    F(0xe7c0, VCLGD,   VRR_a, V,   0, 0, 0, 0, vcdg, 0, IF_VEC)

/* VECTOR FP DIVIDE */

    F(0xe7e5, VFD,     VRR_c, V,   0, 0, 0, 0, vfa, 0, IF_VEC)



#ifndef CONFIG_USER_ONLY

/* COMPARE AND SWAP AND PURGE */

target/s390x/translate_vx.inc.c

+3 −0
Original line number Diff line number Diff line
@@ -2560,6 +2560,9 @@ static DisasJumpType op_vfa(DisasContext *s, DisasOps *o) 
    case 0xe3:

        fn = se ? gen_helper_gvec_vfa64s : gen_helper_gvec_vfa64;

        break;

    case 0xe5:

        fn = se ? gen_helper_gvec_vfd64s : gen_helper_gvec_vfd64;

        break;

    default:

        g_assert_not_reached();

    }

target/s390x/vec_fpu_helper.c

+17 −0
Original line number Diff line number Diff line
@@ -369,3 +369,20 @@ void HELPER(gvec_vclgd64s)(void *v1, const void *v2, CPUS390XState *env, 


    vop64_2(v1, v2, env, true, XxC, erm, vclgd64, GETPC());

}



static uint64_t vfd64(uint64_t a, uint64_t b, float_status *s)

{

    return float64_div(a, b, s);

}



void HELPER(gvec_vfd64)(void *v1, const void *v2, const void *v3,

                        CPUS390XState *env, uint32_t desc)

{

    vop64_3(v1, v2, v3, env, false, vfd64, GETPC());

}



void HELPER(gvec_vfd64s)(void *v1, const void *v2, const void *v3,

                         CPUS390XState *env, uint32_t desc)

{

    vop64_3(v1, v2, v3, env, true, vfd64, GETPC());

}