Commit 09c04e4b authored by David Hildenbrand's avatar David Hildenbrand
Browse files

s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BIT 



Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: default avatarDavid Hildenbrand <david@redhat.com>
parent 35b3bb1c

target/s390x/helper.h

+2 −0
Original line number Diff line number Diff line
@@ -272,6 +272,8 @@ DEF_HELPER_FLAGS_4(gvec_vcdlg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32) 
DEF_HELPER_FLAGS_4(gvec_vcdlg64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)

DEF_HELPER_FLAGS_4(gvec_vcgd64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)

DEF_HELPER_FLAGS_4(gvec_vcgd64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)

DEF_HELPER_FLAGS_4(gvec_vclgd64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)

DEF_HELPER_FLAGS_4(gvec_vclgd64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)



#ifndef CONFIG_USER_ONLY

DEF_HELPER_3(servc, i32, env, i64, i64)

target/s390x/insn-data.def

+2 −0
Original line number Diff line number Diff line
@@ -1224,6 +1224,8 @@ 
    F(0xe7c1, VCDLG,   VRR_a, V,   0, 0, 0, 0, vcdg, 0, IF_VEC)

/* VECTOR FP CONVERT TO FIXED 64-BIT */

    F(0xe7c2, VCGD,    VRR_a, V,   0, 0, 0, 0, vcdg, 0, IF_VEC)

/* VECTOR FP CONVERT TO LOGICAL 64-BIT */

    F(0xe7c0, VCLGD,   VRR_a, V,   0, 0, 0, 0, vcdg, 0, IF_VEC)



#ifndef CONFIG_USER_ONLY

/* COMPARE AND SWAP AND PURGE */

target/s390x/translate_vx.inc.c

+3 −0
Original line number Diff line number Diff line
@@ -2663,6 +2663,9 @@ static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o) 
    case 0xc2:

        fn = se ? gen_helper_gvec_vcgd64s : gen_helper_gvec_vcgd64;

        break;

    case 0xc0:

        fn = se ? gen_helper_gvec_vclgd64s : gen_helper_gvec_vclgd64;

        break;

    default:

        g_assert_not_reached();

    }

target/s390x/vec_fpu_helper.c

+23 −0
Original line number Diff line number Diff line
@@ -346,3 +346,26 @@ void HELPER(gvec_vcgd64s)(void *v1, const void *v2, CPUS390XState *env, 


    vop64_2(v1, v2, env, true, XxC, erm, vcgd64, GETPC());

}



static uint64_t vclgd64(uint64_t a, float_status *s)

{

    return float64_to_uint64(a, s);

}



void HELPER(gvec_vclgd64)(void *v1, const void *v2, CPUS390XState *env,

                          uint32_t desc)

{

    const uint8_t erm = extract32(simd_data(desc), 4, 4);

    const bool XxC = extract32(simd_data(desc), 2, 1);



    vop64_2(v1, v2, env, false, XxC, erm, vclgd64, GETPC());

}



void HELPER(gvec_vclgd64s)(void *v1, const void *v2, CPUS390XState *env,

                           uint32_t desc)

{

    const uint8_t erm = extract32(simd_data(desc), 4, 4);

    const bool XxC = extract32(simd_data(desc), 2, 1);



    vop64_2(v1, v2, env, true, XxC, erm, vclgd64, GETPC());

}