Commit 7b8fe477 authored by Richard Henderson's avatar Richard Henderson Committed by David Gibson
Browse files

target/ppc: convert VSX logical operations to vector operations 



Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Acked-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
Message-Id: <20190215100058.20015-6-mark.cave-ayland@ilande.co.uk>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent 0f6a6d5d

target/ppc/translate/vsx-impl.inc.c

+17 −26
Original line number Diff line number Diff line
@@ -10,6 +10,11 @@ static inline void set_vsr(int n, TCGv_i64 src) 
    tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[n].u64[1]));

}



static inline int vsr_full_offset(int n)

{

    return offsetof(CPUPPCState, vsr[n].u64[0]);

}



static inline void get_cpu_vsrh(TCGv_i64 dst, int n)

{

    if (n < 32) {
@@ -1255,40 +1260,26 @@ static void gen_xxbrw(DisasContext *ctx) 
    tcg_temp_free_i64(xbl);

}



#define VSX_LOGICAL(name, tcg_op)                                    \

#define VSX_LOGICAL(name, vece, tcg_op)                              \

static void glue(gen_, name)(DisasContext * ctx)                     \

    {                                                                \

        TCGv_i64 t0;                                                 \

        TCGv_i64 t1;                                                 \

        TCGv_i64 t2;                                                 \

        if (unlikely(!ctx->vsx_enabled)) {                           \

            gen_exception(ctx, POWERPC_EXCP_VSXU);                   \

            return;                                                  \

        }                                                            \

        t0 = tcg_temp_new_i64();                                     \

        t1 = tcg_temp_new_i64();                                     \

        t2 = tcg_temp_new_i64();                                     \

        get_cpu_vsrh(t0, xA(ctx->opcode));                           \

        get_cpu_vsrh(t1, xB(ctx->opcode));                           \

        tcg_op(t2, t0, t1);                                          \

        set_cpu_vsrh(xT(ctx->opcode), t2);                           \

        get_cpu_vsrl(t0, xA(ctx->opcode));                           \

        get_cpu_vsrl(t1, xB(ctx->opcode));                           \

        tcg_op(t2, t0, t1);                                          \

        set_cpu_vsrl(xT(ctx->opcode), t2);                           \

        tcg_temp_free_i64(t0);                                       \

        tcg_temp_free_i64(t1);                                       \

        tcg_temp_free_i64(t2);                                       \

    }



VSX_LOGICAL(xxland, tcg_gen_and_i64)

VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)

VSX_LOGICAL(xxlor, tcg_gen_or_i64)

VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)

VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)

VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)

VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)

VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)

        tcg_op(vece, vsr_full_offset(xT(ctx->opcode)),               \

               vsr_full_offset(xA(ctx->opcode)),                     \

               vsr_full_offset(xB(ctx->opcode)), 16, 16);            \

    }



VSX_LOGICAL(xxland, MO_64, tcg_gen_gvec_and)

VSX_LOGICAL(xxlandc, MO_64, tcg_gen_gvec_andc)

VSX_LOGICAL(xxlor, MO_64, tcg_gen_gvec_or)

VSX_LOGICAL(xxlxor, MO_64, tcg_gen_gvec_xor)

VSX_LOGICAL(xxlnor, MO_64, tcg_gen_gvec_nor)

VSX_LOGICAL(xxleqv, MO_64, tcg_gen_gvec_eqv)

VSX_LOGICAL(xxlnand, MO_64, tcg_gen_gvec_nand)

VSX_LOGICAL(xxlorc, MO_64, tcg_gen_gvec_orc)



#define VSX_XXMRG(name, high)                               \

static void glue(gen_, name)(DisasContext * ctx)            \