Commit 7777b7a0 authored by Alistair Francis's avatar Alistair Francis Committed by Peter Maydell
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cadence_gem: Correct Marvell PHY SPCFC reset value 



Bit 15 of the PHY Specific Status Register is reserved and
should remain 0. Fix the reset value to ensure that the 15th
bit is not set.

Signed-off-by: default avatarAlistair Francis <alistair.francis@xilinx.com>
Reviewed-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: c795069e49040ff770fe2ece19dfe1791b729e22.1441316450.git.alistair.francis@xilinx.com
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent c96fc9b5

hw/net/cadence_gem.c

+1 −1
Original line number Diff line number Diff line
@@ -951,7 +951,7 @@ static void gem_phy_reset(CadenceGEMState *s) 
    s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00;

    s->phy_regs[PHY_REG_EXTSTAT] = 0x3000;

    s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078;

    s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0xBC00;

    s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00;

    s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60;

    s->phy_regs[PHY_REG_LED] = 0x4100;

    s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A;