Commit c96fc9b5 authored by Edgar E. Iglesias's avatar Edgar E. Iglesias Committed by Peter Maydell
Browse files

target-arm: Add AArch64 access to PAR_EL1 



Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@xilinx.com>
Message-id: 1441311266-8644-4-git-send-email-edgar.iglesias@gmail.com
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 7a379c7e

target-arm/helper.c

+6 −0
Original line number Diff line number Diff line
@@ -2993,6 +2993,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { 
    { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,

      .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },

    { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,

      .type = ARM_CP_ALIAS,

      .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,

      .access = PL1_RW, .resetvalue = 0,

      .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),

      .writefn = par_write },

#endif

    /* TLB invalidate last level of translation table walk */

    { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,