Commit 76e35cc7 authored by David Hildenbrand's avatar David Hildenbrand
Browse files

s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATION 



The only FP instruction we can implement without an helper.

Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: default avatarDavid Hildenbrand <david@redhat.com>
parent c64c5984

target/s390x/insn-data.def

+2 −0
Original line number Diff line number Diff line
@@ -1240,6 +1240,8 @@ 
    F(0xe78f, VFMA,    VRR_e, V,   0, 0, 0, 0, vfma, 0, IF_VEC)

/* VECTOR FP MULTIPLY AND SUBTRACT */

    F(0xe78e, VFMS,    VRR_e, V,   0, 0, 0, 0, vfma, 0, IF_VEC)

/* VECTOR FP PERFORM SIGN OPERATION */

    F(0xe7cc, VFPSO,   VRR_a, V,   0, 0, 0, 0, vfpso, 0, IF_VEC)



#ifndef CONFIG_USER_ONLY

/* COMPARE AND SWAP AND PURGE */

target/s390x/translate_vx.inc.c

+52 −0
Original line number Diff line number Diff line
@@ -2727,3 +2727,55 @@ static DisasJumpType op_vfma(DisasContext *s, DisasOps *o) 
                   0, fn);

    return DISAS_NEXT;

}



static DisasJumpType op_vfpso(DisasContext *s, DisasOps *o)

{

    const uint8_t v1 = get_field(s->fields, v1);

    const uint8_t v2 = get_field(s->fields, v2);

    const uint8_t fpf = get_field(s->fields, m3);

    const uint8_t m4 = get_field(s->fields, m4);

    const uint8_t m5 = get_field(s->fields, m5);

    TCGv_i64 tmp;



    if (fpf != FPF_LONG || extract32(m4, 0, 3) || m5 > 2) {

        gen_program_exception(s, PGM_SPECIFICATION);

        return DISAS_NORETURN;

    }



    if (extract32(m4, 3, 1)) {

        tmp = tcg_temp_new_i64();

        read_vec_element_i64(tmp, v2, 0, ES_64);

        switch (m5) {

        case 0:

            /* sign bit is inverted (complement) */

            tcg_gen_xori_i64(tmp, tmp, 1ull << 63);

            break;

        case 1:

            /* sign bit is set to one (negative) */

            tcg_gen_ori_i64(tmp, tmp, 1ull << 63);

            break;

        case 2:

            /* sign bit is set to zero (positive) */

            tcg_gen_andi_i64(tmp, tmp, (1ull << 63) - 1);

            break;

        }

        write_vec_element_i64(tmp, v1, 0, ES_64);

        tcg_temp_free_i64(tmp);

    } else {

        switch (m5) {

        case 0:

            /* sign bit is inverted (complement) */

            gen_gvec_fn_2i(xori, ES_64, v1, v2, 1ull << 63);

            break;

        case 1:

            /* sign bit is set to one (negative) */

            gen_gvec_fn_2i(ori, ES_64, v1, v2, 1ull << 63);

            break;

        case 2:

            /* sign bit is set to zero (positive) */

            gen_gvec_fn_2i(andi, ES_64, v1, v2, (1ull << 63) - 1);

            break;

        }

    }

    return DISAS_NEXT;

}