Commit 6db06115 authored by Andrea Oliveri's avatar Andrea Oliveri Committed by Aleksandar Markovic
Browse files

target/mips: Enable hardware page table walker and CMGCR features for P5600 



Enable hardware page table walker and CMGCR features for P5600 that
supports both.

Signed-off-by: default avatarAndrea Oliveri <oliveriandrea@gmail.com>
Reviewed-by: default avatarAleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: default avatarAleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <de5adcb9fd0dd607b98026f4bfb34205432b6002.camel@gmail.com>
parent af868995

target/mips/translate_init.inc.c

+5 −4
Original line number Diff line number Diff line
@@ -366,7 +366,7 @@ const mips_def_t mips_defs[] = 
    },

    {

        /* FIXME:

         * Config3: CMGCR, PW, VZ, CTXTC, CDMM, TL

         * Config3: VZ, CTXTC, CDMM, TL

         * Config4: MMUExtDef

         * Config5: MRP

         * FIR(FCR0): Has2008
@@ -380,10 +380,11 @@ const mips_def_t mips_defs[] = 
                       (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |

                       (1 << CP0C1_PC) | (1 << CP0C1_FP),

        .CP0_Config2 = MIPS_CONFIG2,

        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |

        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |

                       (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |

                       (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) |

                       (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1 << CP0C3_LPA) |

                       (1 << CP0C3_VInt),

                       (1 << CP0C3_PW) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |

                       (1 << CP0C3_LPA) | (1 << CP0C3_VInt),

        .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |

                       (0x1c << CP0C4_KScrExist),

        .CP0_Config4_rw_bitmask = 0,