Commit af868995 authored by Huacai Chen's avatar Huacai Chen Committed by Aleksandar Markovic
Browse files

target/mips: Add Loongson-3 CPU definition 



Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and Loongson-3B
R1/R2. Loongson-3A R1 is the oldest and its ISA is the smallest, while
Loongson-3A R4 is the newest and its ISA is almost the superset of all
others. To reduce complexity, we just define two CPU types:

1) "Loongson-3A1000" CPU which is corresponding to Loongson-3A R1. It is
   suitable for TCG because Loongson-3A R1 has fewest ASE.
2) "Loongson-3A4000" CPU which is corresponding to Loongson-3A R4. It is
   suitable for KVM because Loongson-3A R4 has the VZ ASE.

Loongson-3A has CONFIG6 and CONFIG7, so add their bit-fields as well.

[AM: Rearranged insn_flags, added comments, renamed lmi_helper.c,
improved commit message, fixed checkpatch warnings]

Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
Co-developed-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: default avatarAleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: default avatarAleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <1591065557-9174-3-git-send-email-chenhc@lemote.com>
parent 9579f781

target/mips/Makefile.objs

+1 −1
Original line number Diff line number Diff line 
obj-y += translate.o cpu.o gdbstub.o helper.o

obj-y += op_helper.o cp0_helper.o fpu_helper.o

obj-y += dsp_helper.o lmi_helper.o msa_helper.o

obj-y += dsp_helper.o lmmi_helper.o msa_helper.o

obj-$(CONFIG_SOFTMMU) += mips-semi.o

obj-$(CONFIG_SOFTMMU) += machine.o cp0_timer.o

obj-$(CONFIG_KVM) += kvm.o

target/mips/cpu.h

+30 −2
Original line number Diff line number Diff line
@@ -198,8 +198,8 @@ typedef struct mips_def_t mips_def_t; 
 * 3   Config3                             WatchLo3          WatchHi

 * 4   Config4                             WatchLo4          WatchHi

 * 5   Config5                             WatchLo5          WatchHi

 * 6                                       WatchLo6          WatchHi

 * 7                                       WatchLo7          WatchHi

 * 6   Config6                             WatchLo6          WatchHi

 * 7   Config7                             WatchLo7          WatchHi

 *

 *

 *     Register 20       Register 21       Register 22       Register 23
@@ -940,7 +940,35 @@ struct CPUMIPSState { 
#define CP0C5_UFR          2

#define CP0C5_NFExists     0

    int32_t CP0_Config6;

    int32_t CP0_Config6_rw_bitmask;

#define CP0C6_BPPASS          31

#define CP0C6_KPOS            24

#define CP0C6_KE              23

#define CP0C6_VTLBONLY        22

#define CP0C6_LASX            21

#define CP0C6_SSEN            20

#define CP0C6_DISDRTIME       19

#define CP0C6_PIXNUEN         18

#define CP0C6_SCRAND          17

#define CP0C6_LLEXCEN         16

#define CP0C6_DISVC           15

#define CP0C6_VCLRU           14

#define CP0C6_DCLRU           13

#define CP0C6_PIXUEN          12

#define CP0C6_DISBLKLYEN      11

#define CP0C6_UMEMUALEN       10

#define CP0C6_SFBEN           8

#define CP0C6_FLTINT          7

#define CP0C6_VLTINT          6

#define CP0C6_DISBTB          5

#define CP0C6_STPREFCTL       2

#define CP0C6_INSTPREF        1

#define CP0C6_DATAPREF        0

    int32_t CP0_Config7;

    int64_t CP0_Config7_rw_bitmask;

#define CP0C7_NAPCGEN       2

#define CP0C7_UNIMUEN       1

#define CP0C7_VFPUCGEN      0

    uint64_t CP0_LLAddr;

    uint64_t CP0_MAAR[MIPS_MAAR_MAX];

    int32_t CP0_MAARI;

target/mips/internal.h

+2 −0
Original line number Diff line number Diff line
@@ -36,7 +36,9 @@ struct mips_def_t { 
    int32_t CP0_Config5;

    int32_t CP0_Config5_rw_bitmask;

    int32_t CP0_Config6;

    int32_t CP0_Config6_rw_bitmask;

    int32_t CP0_Config7;

    int32_t CP0_Config7_rw_bitmask;

    target_ulong CP0_LLAddr_rw_bitmask;

    int CP0_LLAddr_shift;

    int32_t SYNCI_Step;

target/mips/lmi_helper.c→target/mips/lmmi_helper.c

+0 −0

File moved.

View file

target/mips/mips-defs.h

+25 −20
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ 
 * ------------------------------------------------

 */

/*

 *   bits 0-31: MIPS base instruction sets

 *   bits 0-23: MIPS base instruction sets

 */

#define ISA_MIPS1         0x0000000000000001ULL

#define ISA_MIPS2         0x0000000000000002ULL
@@ -34,30 +34,33 @@ 
#define ISA_MIPS64R6      0x0000000000004000ULL

#define ISA_NANOMIPS32    0x0000000000008000ULL

/*

 *   bits 32-47: MIPS ASEs

 *   bits 24-39: MIPS ASEs

 */

#define ASE_MIPS16        0x0000000100000000ULL

#define ASE_MIPS3D        0x0000000200000000ULL

#define ASE_MDMX          0x0000000400000000ULL

#define ASE_DSP           0x0000000800000000ULL

#define ASE_DSP_R2        0x0000001000000000ULL

#define ASE_DSP_R3        0x0000002000000000ULL

#define ASE_MT            0x0000004000000000ULL

#define ASE_SMARTMIPS     0x0000008000000000ULL

#define ASE_MICROMIPS     0x0000010000000000ULL

#define ASE_MSA           0x0000020000000000ULL

#define ASE_MIPS16        0x0000000001000000ULL

#define ASE_MIPS3D        0x0000000002000000ULL

#define ASE_MDMX          0x0000000004000000ULL

#define ASE_DSP           0x0000000008000000ULL

#define ASE_DSP_R2        0x0000000010000000ULL

#define ASE_DSP_R3        0x0000000020000000ULL

#define ASE_MT            0x0000000040000000ULL

#define ASE_SMARTMIPS     0x0000000080000000ULL

#define ASE_MICROMIPS     0x0000000100000000ULL

#define ASE_MSA           0x0000000200000000ULL

/*

 *   bits 48-55: vendor-specific base instruction sets

 *   bits 40-51: vendor-specific base instruction sets

 */

#define INSN_LOONGSON2E   0x0001000000000000ULL

#define INSN_LOONGSON2F   0x0002000000000000ULL

#define INSN_VR54XX       0x0004000000000000ULL

#define INSN_R5900        0x0008000000000000ULL

#define INSN_VR54XX       0x0000010000000000ULL

#define INSN_R5900        0x0000020000000000ULL

#define INSN_LOONGSON2E   0x0000040000000000ULL

#define INSN_LOONGSON2F   0x0000080000000000ULL

#define INSN_LOONGSON3A   0x0000100000000000ULL

/*

 *   bits 56-63: vendor-specific ASEs

 *   bits 52-63: vendor-specific ASEs

 */

#define ASE_MMI           0x0100000000000000ULL

#define ASE_MXU           0x0200000000000000ULL

#define ASE_MMI           0x0010000000000000ULL

#define ASE_MXU           0x0020000000000000ULL

#define ASE_LMMI          0x0040000000000000ULL

#define ASE_LEXT          0x0080000000000000ULL



/* MIPS CPU defines. */

#define CPU_MIPS1       (ISA_MIPS1)
@@ -94,6 +97,8 @@ 
/* Wave Computing: "nanoMIPS" */

#define CPU_NANOMIPS32  (CPU_MIPS32R6 | ISA_NANOMIPS32)



#define CPU_LOONGSON3A  (CPU_MIPS64R2 | INSN_LOONGSON3A)



/*

 * Strictly follow the architecture standard:

 * - Disallow "special" instruction handling for PMON/SPIM.