Commit 6ab9f499 authored by Edgar E. Iglesias's avatar Edgar E. Iglesias Committed by Peter Maydell
Browse files

target-arm: A64: Fix a typo when declaring TLBI ops 



Harmless typo as opc1 defaults to zero and opc2 gets
re-declared to its correct value.

Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Message-id: 1398926097-28097-4-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 1b505f93

target-arm/helper.c

+12 −12
Original line number Diff line number Diff line
@@ -1908,51 +1908,51 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { 
      .access = PL1_W, .type = ARM_CP_NOP },

    /* TLBI operations */

    { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 0,

      .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,

      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,

      .writefn = tlbiall_write },

    { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 1,

      .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,

      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,

      .writefn = tlbi_aa64_va_write },

    { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 2,

      .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,

      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,

      .writefn = tlbi_aa64_asid_write },

    { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 3,

      .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,

      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,

      .writefn = tlbi_aa64_vaa_write },

    { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 5,

      .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,

      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,

      .writefn = tlbi_aa64_va_write },

    { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 7,

      .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,

      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,

      .writefn = tlbi_aa64_vaa_write },

    { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 0,

      .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,

      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,

      .writefn = tlbiall_write },

    { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 1,

      .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,

      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,

      .writefn = tlbi_aa64_va_write },

    { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 2,

      .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,

      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,

      .writefn = tlbi_aa64_asid_write },

    { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 3,

      .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,

      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,

      .writefn = tlbi_aa64_vaa_write },

    { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 5,

      .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,

      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,

      .writefn = tlbi_aa64_va_write },

    { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 7,

      .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,

      .access = PL1_W, .type = ARM_CP_NO_MIGRATE,

      .writefn = tlbi_aa64_vaa_write },

#ifndef CONFIG_USER_ONLY