Commit 1b505f93 authored by Edgar E. Iglesias's avatar Edgar E. Iglesias Committed by Peter Maydell
Browse files

target-arm: A64: Handle blr lr 



For linked branches, updates to the link register happen
conceptually after the read of the branch target register.

Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Cc: qemu-stable@nongnu.org
Message-id: 1398926097-28097-3-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent fed3ffb9

target-arm/translate-a64.c

+2 −1
Original line number Diff line number Diff line
@@ -1509,8 +1509,10 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) 
    switch (opc) {

    case 0: /* BR */

    case 2: /* RET */

        tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));

        break;

    case 1: /* BLR */

        tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));

        tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);

        break;

    case 4: /* ERET */
@@ -1529,7 +1531,6 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) 
        return;

    }



    tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));

    s->is_jmp = DISAS_JUMP;

}