Commit 6a8d8349 authored by Stefan Hajnoczi's avatar Stefan Hajnoczi
Browse files

Merge remote-tracking branch 'aurel32/tags/pull-target-sh4-20170513' into staging 



Queued target/sh4 patches

# gpg: Signature made Sat 13 May 2017 10:25:41 AM BST
# gpg:                using RSA key 0xBA9C78061DDD8C9B
# gpg: Good signature from "Aurelien Jarno <aurelien@aurel32.net>"
# gpg:                 aka "Aurelien Jarno <aurelien@jarno.fr>"
# gpg:                 aka "Aurelien Jarno <aurel32@debian.org>"
# Primary key fingerprint: 7746 2642 A9EF 94FD 0F77  196D BA9C 7806 1DDD 8C9B

* aurel32/tags/pull-target-sh4-20170513:
  target/sh4: use cpu_loop_exit_restore
  target/sh4: trap unaligned accesses
  target/sh4: movua.l is an SH4-A only instruction
  target/sh4: implement tas.b using atomic helper
  target/sh4: generate fences for SH4
  target/sh4: optimize gen_write_sr using extract op
  target/sh4: optimize gen_store_fpr64
  target/sh4: fold ctx->bstate = BS_BRANCH into gen_conditional_jump
  target/sh4: only save flags state at the end of the TB
  target/sh4: fix BS_EXCP exit
  target/sh4: fix BS_STOP exit
  target/sh4: move DELAY_SLOT_TRUE flag into a separate global
  target/sh4: do not include DELAY_SLOT_TRUE in the TB state
  target/sh4: get rid of DELAY_SLOT_CLEARME
  target/sh4: split ctx->flags into ctx->tbflags and ctx->envflags

Signed-off-by: default avatarStefan Hajnoczi <stefanha@redhat.com>
parents eba01619 57e2d417

target/sh4/cpu.c

+1 −0
Original line number Diff line number Diff line
@@ -301,6 +301,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) 
#ifdef CONFIG_USER_ONLY

    cc->handle_mmu_fault = superh_cpu_handle_mmu_fault;

#else

    cc->do_unaligned_access = superh_cpu_do_unaligned_access;

    cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;

#endif

    cc->disas_set_info = superh_cpu_disas_set_info;

target/sh4/cpu.h

+7 −11
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
#include "cpu-qom.h"



#define TARGET_LONG_BITS 32

#define ALIGNED_ONLY



/* CPU Subtypes */

#define SH_CPU_SH7750  (1 << 0)
@@ -92,14 +93,6 @@ 


#define DELAY_SLOT             (1 << 0)

#define DELAY_SLOT_CONDITIONAL (1 << 1)

#define DELAY_SLOT_TRUE        (1 << 2)

#define DELAY_SLOT_CLEARME     (1 << 3)

/* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump

 * after the delay slot should be taken or not. It is calculated from SR_T.

 *

 * It is unclear if it is permitted to modify the SR_T flag in a delay slot.

 * The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification.

 */



typedef struct tlb_t {

    uint32_t vpn;		/* virtual page number */
@@ -149,7 +142,8 @@ typedef struct CPUSH4State { 
    uint32_t sgr;		/* saved global register 15 */

    uint32_t dbr;		/* debug base register */

    uint32_t pc;		/* program counter */

    uint32_t delayed_pc;	/* target of delayed jump */

    uint32_t delayed_pc;        /* target of delayed branch */

    uint32_t delayed_cond;      /* condition of delayed branch */

    uint32_t mach;		/* multiply and accumulate high */

    uint32_t macl;		/* multiply and accumulate low */

    uint32_t pr;		/* procedure register */
@@ -222,6 +216,9 @@ void superh_cpu_dump_state(CPUState *cpu, FILE *f, 
hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

int superh_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);

int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);

void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,

                                    MMUAccessType access_type,

                                    int mmu_idx, uintptr_t retaddr);



void sh4_translate_init(void);

SuperHCPU *cpu_sh4_init(const char *cpu_model);
@@ -383,8 +380,7 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc, 
{

    *pc = env->pc;

    *cs_base = 0;

    *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL

                    | DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME))   /* Bits  0- 3 */

    *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) /* Bits 0-1 */

            | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR))  /* Bits 19-21 */

            | (env->sr & ((1u << SR_MD) | (1u << SR_RB)))      /* Bits 29-30 */

            | (env->sr & (1u << SR_FD))                        /* Bit 15 */

target/sh4/helper.c

+1 −3
Original line number Diff line number Diff line
@@ -168,10 +168,8 @@ void superh_cpu_do_interrupt(CPUState *cs) 
        /* Branch instruction should be executed again before delay slot. */

	env->spc -= 2;

	/* Clear flags for exception/interrupt routine. */

	env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE);

        env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);

    }

    if (env->flags & DELAY_SLOT_CLEARME)

        env->flags = 0;



    if (do_exp) {

        env->expevt = cs->exception_index;

target/sh4/op_helper.c

+18 −8
Original line number Diff line number Diff line
@@ -24,6 +24,22 @@ 


#ifndef CONFIG_USER_ONLY



void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr,

                                    MMUAccessType access_type,

                                    int mmu_idx, uintptr_t retaddr)

{

    switch (access_type) {

    case MMU_INST_FETCH:

    case MMU_DATA_LOAD:

        cs->exception_index = 0x0e0;

        break;

    case MMU_DATA_STORE:

        cs->exception_index = 0x100;

        break;

    }

    cpu_loop_exit_restore(cs, retaddr);

}



void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,

              int mmu_idx, uintptr_t retaddr)

{
@@ -32,10 +48,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, 
    ret = superh_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx);

    if (ret) {

        /* now we have a real cpu fault */

        if (retaddr) {

            cpu_restore_state(cs, retaddr);

        }

        cpu_loop_exit(cs);

        cpu_loop_exit_restore(cs, retaddr);

    }

}
@@ -59,10 +72,7 @@ static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index, 
    CPUState *cs = CPU(sh_env_get_cpu(env));



    cs->exception_index = index;

    if (retaddr) {

        cpu_restore_state(cs, retaddr);

    }

    cpu_loop_exit(cs);

    cpu_loop_exit_restore(cs, retaddr);

}



void helper_raise_illegal_instruction(CPUSH4State *env)

target/sh4/translate.c

+154 −168

File changed.

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