Commit eba01619 authored by Stefan Hajnoczi's avatar Stefan Hajnoczi
Browse files

Merge remote-tracking branch 'rth/tags/pull-s390-20170512' into staging 



Queued target/s390 patches

# gpg: Signature made Sat 13 May 2017 12:33:08 AM BST
# gpg:                using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg:                 aka "Richard Henderson <rth@redhat.com>"
# gpg:                 aka "Richard Henderson <rth@twiddle.net>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC  16A4 AD12 70CC 4DD0 279B

* rth/tags/pull-s390-20170512:
  target/s390x: implement serialization in BRANCH CONDITION
  target/s390x: fix SIGNAL PROCESSOR return value
  target/s390x: mask the SIGP order_code using SIGP_ORDER_MASK
  target/s390x: Use atomic operations for LOAD AND OP
  target/s390x: Use atomic operations for COMPARE SWAP
  target/s390x: Implement LOAD PAIR DISJOINT
  target/s390x: Diagnose specification exception for atomics
  target/s390x: Implement LOAD PROGRAM PARAMETER
  target/s390x: Implement STORE FACILITIES LIST EXTENDED

Signed-off-by: default avatarStefan Hajnoczi <stefanha@redhat.com>
parents 8a813c98 538fad59

target/s390x/cpu.c

+1 −0
Original line number Diff line number Diff line
@@ -430,6 +430,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) 
    cc->write_elf64_note = s390_cpu_write_elf64_note;

    cc->cpu_exec_interrupt = s390_cpu_exec_interrupt;

    cc->debug_excp_handler = s390x_cpu_debug_excp_handler;

    cc->do_unaligned_access = s390x_cpu_do_unaligned_access;

#endif

    cc->disas_set_info = s390_cpu_disas_set_info;

target/s390x/cpu.h

+6 −0
Original line number Diff line number Diff line
@@ -480,6 +480,9 @@ int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, 


#ifndef CONFIG_USER_ONLY

void do_restart_interrupt(CPUS390XState *env);

void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,

                                   MMUAccessType access_type,

                                   int mmu_idx, uintptr_t retaddr);



static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb,

                                       uint8_t *ar)
@@ -1075,6 +1078,9 @@ struct sysib_322 { 
#define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1

#define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2



/* SIGP order code mask corresponding to bit positions 56-63 */

#define SIGP_ORDER_MASK 0x000000ff



void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);

int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,

                  target_ulong *raddr, int *flags, bool exc);

target/s390x/helper.c

+16 −0
Original line number Diff line number Diff line
@@ -718,4 +718,20 @@ void s390x_cpu_debug_excp_handler(CPUState *cs) 
        cpu_loop_exit_noexc(cs);

    }

}



/* Unaligned accesses are only diagnosed with MO_ALIGN.  At the moment,

   this is only for the atomic operations, for which we want to raise a

   specification exception.  */

void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,

                                   MMUAccessType access_type,

                                   int mmu_idx, uintptr_t retaddr)

{

    S390CPU *cpu = S390_CPU(cs);

    CPUS390XState *env = &cpu->env;



    if (retaddr) {

        cpu_restore_state(cs, retaddr);

    }

    program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER);

}

#endif /* CONFIG_USER_ONLY */

target/s390x/helper.h

+3 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ DEF_HELPER_3(cxgb, i64, env, s64, i32) 
DEF_HELPER_3(celgb, i64, env, i64, i32)

DEF_HELPER_3(cdlgb, i64, env, i64, i32)

DEF_HELPER_3(cxlgb, i64, env, i64, i32)

DEF_HELPER_4(cdsg, void, env, i64, i32, i32)

DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64)

DEF_HELPER_FLAGS_3(adb, TCG_CALL_NO_WG, i64, env, i64, i64)

DEF_HELPER_FLAGS_5(axb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64)
@@ -83,6 +84,8 @@ DEF_HELPER_FLAGS_5(calc_cc, TCG_CALL_NO_RWG_SE, i32, env, i32, i64, i64, i64) 
DEF_HELPER_FLAGS_2(sfpc, TCG_CALL_NO_RWG, void, env, i64)

DEF_HELPER_FLAGS_2(sfas, TCG_CALL_NO_WG, void, env, i64)

DEF_HELPER_FLAGS_1(popcnt, TCG_CALL_NO_RWG_SE, i64, i64)

DEF_HELPER_FLAGS_1(stfl, TCG_CALL_NO_RWG, void, env)

DEF_HELPER_2(stfle, i32, env, i64)



#ifndef CONFIG_USER_ONLY

DEF_HELPER_3(servc, i32, env, i64, i64)

target/s390x/insn-data.def

+22 −16
Original line number Diff line number Diff line
@@ -239,12 +239,12 @@ 
    D(0xec7d, CLGIJ,   RIE_c, GIE, r1_o, i2_8u, 0, 0, cj, 0, 1)



/* COMPARE AND SWAP */

    D(0xba00, CS,      RS_a,  Z,   r3_32u, r1_32u, new, r1_32, cs, 0, 0)

    D(0xeb14, CSY,     RSY_a, LD,  r3_32u, r1_32u, new, r1_32, cs, 0, 0)

    D(0xeb30, CSG,     RSY_a, Z,   r3_o, r1_o, new, r1, cs, 0, 1)

    D(0xba00, CS,      RS_a,  Z,   r3_32u, r1_32u, new, r1_32, cs, 0, MO_TEUL)

    D(0xeb14, CSY,     RSY_a, LD,  r3_32u, r1_32u, new, r1_32, cs, 0, MO_TEUL)

    D(0xeb30, CSG,     RSY_a, Z,   r3_o, r1_o, new, r1, cs, 0, MO_TEQ)

/* COMPARE DOUBLE AND SWAP */

    D(0xbb00, CDS,     RS_a,  Z,   r3_D32, r1_D32, new, r1_D32, cs, 0, 1)

    D(0xeb31, CDSY,    RSY_a, LD,  r3_D32, r1_D32, new, r1_D32, cs, 0, 1)

    D(0xbb00, CDS,     RS_a,  Z,   r3_D32, r1_D32, new, r1_D32, cs, 0, MO_TEQ)

    D(0xeb31, CDSY,    RSY_a, LD,  r3_D32, r1_D32, new, r1_D32, cs, 0, MO_TEQ)

    C(0xeb3e, CDSG,    RSY_a, Z,   0, 0, 0, 0, cdsg, 0)



/* COMPARE AND TRAP */
@@ -390,20 +390,20 @@ 
/* LOAD ADDRESS RELATIVE LONG */

    C(0xc000, LARL,    RIL_b, Z,   0, ri2, 0, r1, mov2, 0)

/* LOAD AND ADD */

    C(0xebf8, LAA,     RSY_a, ILA, r3_32s, m2_32s_atomic, new, m2_32_r1_atomic, add, adds32)

    C(0xebe8, LAAG,    RSY_a, ILA, r3, m2_64_atomic, new, m2_64_r1_atomic, add, adds64)

    D(0xebf8, LAA,     RSY_a, ILA, r3_32s, a2, new, in2_r1_32, laa, adds32, MO_TESL)

    D(0xebe8, LAAG,    RSY_a, ILA, r3, a2, new, in2_r1, laa, adds64, MO_TEQ)

/* LOAD AND ADD LOGICAL */

    C(0xebfa, LAAL,    RSY_a, ILA, r3_32s, m2_32s_atomic, new, m2_32_r1_atomic, add, addu32)

    C(0xebea, LAALG,   RSY_a, ILA, r3, m2_64_atomic, new, m2_64_r1_atomic, add, addu64)

    D(0xebfa, LAAL,    RSY_a, ILA, r3_32u, a2, new, in2_r1_32, laa, addu32, MO_TEUL)

    D(0xebea, LAALG,   RSY_a, ILA, r3, a2, new, in2_r1, laa, addu64, MO_TEQ)

/* LOAD AND AND */

    C(0xebf4, LAN,     RSY_a, ILA, r3_32s, m2_32s_atomic, new, m2_32_r1_atomic, and, nz32)

    C(0xebe4, LANG,    RSY_a, ILA, r3, m2_64_atomic, new, m2_64_r1_atomic, and, nz64)

    D(0xebf4, LAN,     RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lan, nz32, MO_TESL)

    D(0xebe4, LANG,    RSY_a, ILA, r3, a2, new, in2_r1, lan, nz64, MO_TEQ)

/* LOAD AND EXCLUSIVE OR */

    C(0xebf7, LAX,     RSY_a, ILA, r3_32s, m2_32s_atomic, new, m2_32_r1_atomic, xor, nz32)

    C(0xebe7, LAXG,    RSY_a, ILA, r3, m2_64_atomic, new, m2_64_r1_atomic, xor, nz64)

    D(0xebf7, LAX,     RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lax, nz32, MO_TESL)

    D(0xebe7, LAXG,    RSY_a, ILA, r3, a2, new, in2_r1, lax, nz64, MO_TEQ)

/* LOAD AND OR */

    C(0xebf6, LAO,     RSY_a, ILA, r3_32s, m2_32s_atomic, new, m2_32_r1_atomic, or, nz32)

    C(0xebe6, LAOG,    RSY_a, ILA, r3, m2_64_atomic, new, m2_64_r1_atomic, or, nz64)

    D(0xebf6, LAO,     RSY_a, ILA, r3_32s, a2, new, in2_r1_32, lao, nz32, MO_TESL)

    D(0xebe6, LAOG,    RSY_a, ILA, r3, a2, new, in2_r1, lao, nz64, MO_TEQ)

/* LOAD AND TEST */

    C(0x1200, LTR,     RR_a,  Z,   0, r2_o, 0, cond_r1r2_32, mov2, s32)

    C(0xb902, LTGR,    RRE,   Z,   0, r2_o, 0, r1, mov2, s64)
@@ -504,7 +504,9 @@ 
    C(0xb9e2, LOCGR,   RRF_c, LOC, r1, r2, r1, 0, loc, 0)

    C(0xebf2, LOC,     RSY_b, LOC, r1, m2_32u, new, r1_32, loc, 0)

    C(0xebe2, LOCG,    RSY_b, LOC, r1, m2_64, r1, 0, loc, 0)

/* LOAD PAIR DISJOINT TODO */

/* LOAD PAIR DISJOINT */

    D(0xc804, LPD,     SSF,   ILA, 0, 0, new_P, r3_P32, lpd, 0, MO_TEUL)

    D(0xc805, LPDG,    SSF,   ILA, 0, 0, new_P, r3_P64, lpd, 0, MO_TEQ)

/* LOAD POSITIVE */

    C(0x1000, LPR,     RR_a,  Z,   0, r2_32s, new, r1_32, abs, abs32)

    C(0xb900, LPGR,    RRE,   Z,   0, r2, r1, 0, abs, abs64)
@@ -747,6 +749,8 @@ 
    C(0xe33e, STRV,    RXY_a, Z,   la2, r1_32u, new, m1_32, rev32, 0)

    C(0xe32f, STRVG,   RXY_a, Z,   la2, r1_o, new, m1_64, rev64, 0)



/* STORE FACILITY LIST EXTENDED */

    C(0xb2b0, STFLE,   S,  SFLE,   0, a2, 0, 0, stfle, 0)

/* STORE FPC */

    C(0xb29c, STFPC,   S,     Z,   0, a2, new, m2_32, efpc, 0)
@@ -843,6 +847,8 @@ 
/* LOAD CONTROL */

    C(0xb700, LCTL,    RS_a,  Z,   0, a2, 0, 0, lctl, 0)

    C(0xeb2f, LCTLG,   RSY_a, Z,   0, a2, 0, 0, lctlg, 0)

/* LOAD PROGRAM PARAMETER */

    C(0xb280, LPP,     S,   LPP,   0, m2_64, 0, 0, lpp, 0)

/* LOAD PSW */

    C(0x8200, LPSW,    S,     Z,   0, a2, 0, 0, lpsw, 0)

/* LOAD PSW EXTENDED */