Unverified Commit 6591efb5 authored by Philippe Mathieu-Daudé's avatar Philippe Mathieu-Daudé Committed by Palmer Dabbelt
Browse files

target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events 



Use the always-compiled trace events, remove the now unused
RISCV_DEBUG_PMP definition.

Note pmpaddr_csr_read() could previously do out-of-bound accesses
passing addr_index >= MAX_RISCV_PMPS.

Signed-off-by: default avatarPhilippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent 0b84b662

target/riscv/pmp.c

+10 −21
Original line number Diff line number Diff line
@@ -27,14 +27,7 @@ 
#include "qemu/log.h"

#include "qapi/error.h"

#include "cpu.h"



#define RISCV_DEBUG_PMP 0

#define PMP_DEBUG(fmt, ...)                                                    \

    do {                                                                       \

        if (RISCV_DEBUG_PMP) {                                                 \

            qemu_log_mask(LOG_TRACE, "%s: " fmt "\n", __func__, ##__VA_ARGS__);\

        }                                                                      \

    } while (0)

#include "trace.h"



static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,

    uint8_t val);
@@ -302,8 +295,7 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, 
    int i;

    uint8_t cfg_val;



    PMP_DEBUG("hart " TARGET_FMT_ld ": reg%d, val: 0x" TARGET_FMT_lx,

        env->mhartid, reg_index, val);

    trace_pmpcfg_csr_write(env->mhartid, reg_index, val);



    if ((reg_index & 1) && (sizeof(target_ulong) == 8)) {

        qemu_log_mask(LOG_GUEST_ERROR,
@@ -332,9 +324,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) 
        val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i);

        cfg_val |= (val << (i * 8));

    }



    PMP_DEBUG("hart " TARGET_FMT_ld ": reg%d, val: 0x" TARGET_FMT_lx,

        env->mhartid, reg_index, cfg_val);

    trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val);



    return cfg_val;

}
@@ -346,9 +336,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) 
void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,

    target_ulong val)

{

    PMP_DEBUG("hart " TARGET_FMT_ld ": addr%d, val: 0x" TARGET_FMT_lx,

        env->mhartid, addr_index, val);



    trace_pmpaddr_csr_write(env->mhartid, addr_index, val);

    if (addr_index < MAX_RISCV_PMPS) {

        if (!pmp_is_locked(env, addr_index)) {

            env->pmp_state.pmp[addr_index].addr_reg = val;
@@ -369,14 +357,15 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, 
 */

target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)

{

    PMP_DEBUG("hart " TARGET_FMT_ld ": addr%d, val: 0x" TARGET_FMT_lx,

        env->mhartid, addr_index,

        env->pmp_state.pmp[addr_index].addr_reg);

    target_ulong val = 0;



    if (addr_index < MAX_RISCV_PMPS) {

        return env->pmp_state.pmp[addr_index].addr_reg;

        val = env->pmp_state.pmp[addr_index].addr_reg;

        trace_pmpaddr_csr_read(env->mhartid, addr_index, val);

    } else {

        qemu_log_mask(LOG_GUEST_ERROR,

                      "ignoring pmpaddr read - out of bounds\n");

        return 0;

    }



    return val;

}

target/riscv/trace-events

+6 −0
Original line number Diff line number Diff line 
# target/riscv/cpu_helper.c

riscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t tval, const char *desc) "hart:%"PRId64", async:%d, cause:%"PRId64", epc:0x%"PRIx64", tval:0x%"PRIx64", desc=%s"



# pmp.c

pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": read reg%" PRIu32", val: 0x%" PRIx64

pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": write reg%" PRIu32", val: 0x%" PRIx64

pmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": read addr%" PRIu32", val: 0x%" PRIx64

pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": write addr%" PRIu32", val: 0x%" PRIx64